ZuoTi.Pro
Question

This problem concerns a physical memory cache. Recall that m is the number of physical address...

This problem concerns a physical memory cache. Recall that m is the number of physical address bits, C is the cache size (number of bytes), B is the block size in bytes, E is the associativity, S is the number of cache sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Suppose we have a cache with the following characteristics m = 32 C = 2048 S = 128 t =23 s = 7 b = 2 What is the value of B?

engineering   Computer-Science   
0 0
Add a comment Improve this question Transcribed image text
Next > < Previous
Sort answers by oldest

Homework Answers

Answer #1

Here in the question the block offset bits are 2 ,

so the block size B = 2^2= 4bytes.

Thank you.

0 0
Add a comment
Know the answer?
Add Answer to:
This problem concerns a physical memory cache. Recall that m is the number of physical address...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Log In

Sign Up

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions

  • A primary memory system consists of 128 address bits. Each block within the cache is 256...

    A primary memory system consists of 128 address bits. Each block within the cache is 256 bytes. The total cache size is 131,072 bytes. What are the sizes of the tag and index in the cache? First, find the number of blocks. 128,000 bytes # Blocks = 256 bytes per block bort = 512 blocks Where does the 128,000 come from?? Now find the number of bits required to distinguish all the blocks. This is the index aka set size....

  • Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a...

    Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a 32 blocks direct mapped cache. The cache is initially empty. The following decimal memory addresses are referenced 1020, 1006, 1022, 5106, 994, and 2019 Map the addresses to cache blocks and indicate whether hit or miss. Note: You must use the hexadecimal approach in solving this question. You must also show the computations of dividing the memory address into tag bits, cache index bits,...

  • question 2 and 3 2. Determine how many sets of cache blocks will be there for...

    question 2 and 3 2. Determine how many sets of cache blocks will be there for the following Cache memory size (in bytes) Direct Mapped Blocks Size (in bits) 32 64 218 2-way Set Associative Block Size (in bits) 32 64 A 2A6 [0.5 * 16 = 8] 4-way Set Associative Block Size (in bits) 32 64 SK 64K 256K 3. The physical memory address generated by a CPU is converted into cache memory addressing scheme using the following mapping...

  • 32 bytes of memory. 16 bytes of 2-way setassociative cache, where blocks can go anywhere within...

    32 bytes of memory. 16 bytes of 2-way setassociative cache, where blocks can go anywhere within the set. Block is 4 bytes, set in cache is two blocks. Populate memory starting with 0-9, then upper case letters. Hint- with full associativity in the set: each block has its own set of Tag bits in the cache. Memory is not organized by sets, though blocks get assigned to sets, and load in the cache per set. A) Complete: Bits in Address...

  • Question 6 For the following figure shows a hypothetical memory hierarchy going from a virtual address to L2 cache acce...

    Question 6 For the following figure shows a hypothetical memory hierarchy going from a virtual address to L2 cache access. The page size is 8KB, the TLB is direct mapped with 128 entries. The L1 cache is a direct mapped 8 KB, and the L2 cache is 2MB and direct mapped. Both use 64 byte blocks. The virtual address is 64 bits and the physical address is 41 bits. For each block in the figure below, fill in the number...

  • The physical address of memory on a machine is 32 bits. The machine has a direct...

    The physical address of memory on a machine is 32 bits. The machine has a direct mapped cache of size 512 KB with a block size of 8 bytes. What is the size of the tag field in bits? Can you please explain this step by step and what the importance of direct mapped is?

  • For a 16K-byte, direct-mapped cache, suppose the block size is 32 bytes, draw a cache diagram....

    For a 16K-byte, direct-mapped cache, suppose the block size is 32 bytes, draw a cache diagram. Indicate the block size, number of blocks, and address field decomposition (block offset, index, and tag bit width) assuming a 32-bit memory address.

  • 32 bytes of memory. 16 bytes of 2-way set-associative cache, where blocks can go anywhere within...

    32 bytes of memory. 16 bytes of 2-way set-associative cache, where blocks can go anywhere within the set. Block is 2 bytes, set in cache is two blocks. Populate memory starting with upper-case letters, then 0-5. Hint- with full associativity in the set: each block has its own set of Tag bits in the cache. Memory is not organized by sets, though blocks get assigned to sets, and load in the cache per set.
1) Break down the addressing: Tag...

  • If you were to build the cache memory from problem 1 (provided below), what is the...

    If you were to build the cache memory from problem 1 (provided below), what is the total size (in bytes) required for this cache memory? The total size includes data, tag, and valid bit chips. Hint: your solution might not be a power of 2. Total cache memory is 128k bytes Cache block size is 4 words (1 word = 4 bytes) CPU address window = 32 bits Cache memory chip size = 4k x 8-bits

  • Problem 6. Suppose we have a computer with 32 megabytes of main memory, 256 bytes of...

    Problem 6. Suppose we have a computer with 32 megabytes of main memory, 256 bytes of cache, and a block size of 16 bytes. For each configuration below, determine the memory address format, indicating the number of bits needed for each appropriate field (i.e. tag, block, set, offset). Show any relevant calculations. Direct cache mapping and memory is byte-addressable a) Direct cache mapping and memory is word-addressable with a word size of 16 bits b) c) 2-way set associative cache...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT