A high voltage busbar is protected by a high-impedance differential relay as shown in the following figure. For an external faulton line L4 very close to the busbar, theresultingprimary fault current (in kA) on eachline is indicated in the diagram. Assume
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A high voltage busbar is protected by a high-impedance differential relay as shown in the following figure. For an external faulton line L4 very close to the busbar, theresultingprimary fault current (in kA) on eachline is indicated in the diagram. Assume
Calculate the apparent impedance seen by a distance relay at terminal X for a three terminal line with the following impedance and fault current values. The fault is at terminal Y. State any assumption you make.
Consider the system Shown in the single-line diagram of Figure (3). All reactance are shown in per unit to the same base. Assume that the voltage at both sources is 1 p.u.
Consider the system shown in the single-line diagram of Figure (3). All reactances are shown in per unit to the same base. Assume that the voltage at both sources is \(1 \mathrm{p}\).u.
a- Find the fault current due to a bolted- three-phase short circuit at bus \(3 .[10\) points \(]\)
b- Find the fault current supplied by each generator and the voltage at each of the buses 1 and 2 under fault conditions. \([10\) points \(]\)
Consider the system Shown in the single-line diagram of Figure (3). All reactance are shown in per unit to the same base. Assume that the voltage at both sources is 1 p.u.
Consider the system Shown in the single-line diagram of Figure (2). All reactance are shown in per unit to the same base. Assume that the voltage at both sources is 1 p.u.
Draw a per unit impedance diagram for the system whose one-line diagram shown in Fig.1. The three phases and line-to-line ratings are as given in the figure. Assume the load is a parallel combination of Resistance and reactance (R&X). Select a base of 100
Problem 3. (25 pts) The timing diagram for three state cases represents the high impedance state with a line between the low (0) and high (0) states, as ill figure: ustrated in the following 0 L...
Problem 3. (25 pts) The timing diagram for three state cases represents the high impedance state with a line between the low (0) and high (0) states, as ill figure: ustrated in the following 0 Low (0) High Impedance (Z)1 High (1) a. (15 pts) Draw the timing diagrams for the outputs A,B,C,D of the following circuit given the input diagrams in the next page. (NOTE: to help you, dashed lines are shown for the different levels) b. (10 pts)...
Problem 3. (25 pts) The timing diagram for three state cases represents the high impedance state with a line between the low (0) and high (0) states, as ill figure: ustrated in the following 0 Low (0) High Impedance (Z)1 High (1) a. (15 pts) Draw the timing diagrams for the outputs A,B,C,D of the following circuit given the input diagrams in the next page. (NOTE: to help you, dashed lines are shown for the different levels) b. (10 pts)...
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