Question

show its derivation to get the full mark. 2. (10 marks) 0 3 Figure 2: Mapping from input bits to different LED segments on a SSD Design a structural System Verilog module for a 7 segment display decoder that has a four bit input C, and produces a seven bit outpt Y which can be used to display the character associated with the hexadecimal value of C on a 7-segment display. The seven segments in the display are identified with the bits of Y by the indices 0 to 6 shown in Figure 2. Each segment is illuminated by driving the corresponding bit to the logic value 0 Instantiate your seven segment decoder module on the DE2 board, and connect it with the switches and the seven segment displays to verify its functionality To design the structural module you are required to carry out Boolean simplification, e.g., by using Karnaugh maps. Please show your calculations clearly in the report Marking Criteria: . Functionality (3) The circuit must be fully functional to get 5/5. For partially func- tional circuit your mark will depend on the results achieved. . Design efficiency (4) - To get 4/4 you should be able to show that your design uses the smallest number of logic gates. The mark for a less efficient design will depend on how bulky it is. . Design steps and methodology (3) - To get 3/3 you must clearly show the steps used to simplfy the logic.

Answer 1

Seven segment display decoder design: step(1): don't cares *Note: The truth table is construction based on assumption that the LED'S are illuminated by driving the logic value '0' simply find thee values of y[0] to y[6] using k-map simply find the values the negotiation to the individual inputs that is from y[0] to y[6], the procedure is as follows: Y[0] = C[3] + C[1] + C[0]^bar C[2]^bar + C[0] c[2] Y[0] = C[3] + C[1] + C[0] dotcircled [C2] As the LED's has to blink for corresponding logic 0 Y[0] = ~ Y[0] Y[0] = ~ [C[3] + C[1] + C[0] dotcircled C[2]]