Question

(10 pts.): The component AC specifications below apply to the datapath from Question 2. Assume routing delays are negligible, and the paths that include the interface data and control signals have no timing marginality. Show all details of your analysis in answering the below questions for full credit. START Data In (1:0) #25 1 0 SELECT SO LOAD EN 2-Bit Loadable Shift Register A 210 SI 2-Bit Shift Register B SHF SHF SHIFT Control Unit STOP Adder 72 DataOut (2:0) Component AC Timing Specifications (all values in ps) Combinational to-min Synchronous tp-min to-max tsu tho Adder 220 Register A 70 120 60 | 4-to-1 MUX I 20 30 Parallel Load Ip-max 340 30 Register A and B Shift 50 100 20 10 a. (5 pts.) What is the maximum possible clock frequency, fmax, that ensures correct data transfer among the datapath registers in this circuit? b. (5 pts.) What is the worst case hold-timing slack in the circuit?

Answer 1

Sol: @In the Guven Circuit there are a major resistor to resis for paths (long delay) Path 0 Load - Adder mux Capture FF = load load Adder mux IP (max) = 120+ 340 + 300 = 49ops Path & Shift Adder – max load Capture FF = load Shift Adder 100+ 340 + 3 mus 0 tplmay) - = 470ps. Path has maximum delay i Talk > tp (max) + tsetup of Capture FF Talk 490 +60 ) Tak > 550ps minimum clock period Maximum clock frequency - Faire = 560 X 10-12 max ferk = 1.818 GHZ 6 Hold slack us nothing but difference of data arrival time and data required time There us a direct path thetween load and shift register which act as minimum delay path toimin) = tp-min of load & Tops Here capture FF us shift Register lops Hold slack-toimins - thold - 70-10=60p Hold slack = 60ps