Question

Create the VHDL model of a digital system that has outputs CC0 to CC7. Each output is active (logic 1) for one clock period in successive clock cycles. The outputs are all mutually exclusive when they are active, i.e. when one is logic I all others are logic 0. The block diagram and sample timing diagram of the system are shown below. After CC7 becomes logic 1, this pattern repeats by having CCO as logic 1 in the next clock cycle. The Reset input will take the system to an initial state where all outputs are zero. You may use behavioral or structural style of coding to develop the VHDL model. CLK еф Г Rext cca т cal CC2 -occ3 Cc4 CC ce2 CLK к нссе Сс hoca

Answer 1

VHDL module:

here we can use the shifter:

10000000 (at the start is rotated to the right ).

and the output reset to outputs 0.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library ieee;
--use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity circuit IS
port( clk: in std_logic;-- 1hz clock
reset: in std_logic;--input
cc: out std_logic_vector(7 downto 0)-- output 4 bit wide
);
end circuit;

architecture logic11 of circuit is
begin
process(clk)
variable reg: std_logic_vector(2 downto 0):="000";
begin
if (clk'event and clk = '1') then -- otherwise update the states
if (reset = '1') then -- go to state zero if reset
reg:="UUU";-- set to use default of case to set output to 0.
else
reg:=reg+1; -- counter to count for each clock pulse
end if;
case reg is -- for output definations
when "000" =>
cc <= "10000000";
when "001" =>
cc <= "01000000";
when "010" =>
cc <= "00100000";
when "011" =>
cc <= "00010000";
when "100" =>
cc <= "00001000";
when "101" =>
cc <= "00000100";
when "110" =>
cc <= "00000010";
when "111" =>
cc <= "00000001";
when others => -- for Reset
cc <="00000000";
end case;
else
null;
end if;
end process;
end logic11;