Homework Answers
RISC-V instruction is 4 byte format for any instruction. Memory is big-endian which means that lower byte of instruction code is stored at higher address.
It means -
- 0x00408000 => 0x00 (3rd Byte)
- 0x00408001 => 0x87 (2nd Byte)
- 0x00408002 => 0x1D (1st Byte)
- 0x00408003 => 0x93 (0th Byte)
So, the assembly instruction stored at address 0x00408000 is 0x00871D93
0x00871D93
Binary Code => 0000 0000 1000 0111 0001 1101 1001 0011
Each RISC-V Instruction has right most 7 bits for opcode.
- Opcode = 0010011 (I-Type Instruction)
Opcode 0010011 represents I-Type operations. Format for I-type RISC-V instruction is as below.
![31 R I 27 26 25 24 20 19 15 funct7 rs2 rs1 imm[11:0] rs1 imm[11:5] rs2 rs1 imm[12|10:5] rs2 rs1 imm[31:12] imm[20|10:1|11|19:](http://img.homeworklib.com/questions/f29e7be0-aabe-11eb-aef7-31170effd783.png?x-oss-process=image/resize,w_560)
- rs1 = 01110 = x14 (Source Register 1)
- func3 = 001
- It means the actual operation is SLLI based on table below.
- rd = 11011 = x27 (Destination Register)
- Opcode = 0010011
- imm [11:0] = 000000001000
- Divided into two parts
- Fixed bits = 0000000
- Shamt (shift value) = 01000 = 8 (decimal)
![rs 1 rs1 rs 1 rs1 imm[11:0) imm[11:0) imm[11:0] imm[11:0) imm[11:07 imm[11:0) 0000000 0000000 000 010 011 100 110 111 001 101](http://img.homeworklib.com/questions/f3323e60-aabe-11eb-9946-83c74beb3491.png?x-oss-process=image/resize,w_560)
So, Final instruction is Shift Left Logical
SLLI x27, x14, 8 => (x27 = x14 << 8)
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