ZuoTi.Pro
Question

1. A system with a word length of 32-bit and byte-addressable memory has ten consecutive 32-bit signed numbers stored startin

engineering   Computer-Science   
0 0
Add a comment Improve this question Transcribed image text
Next > < Previous
Sort answers by oldest

Homework Answers

Answer #1

Greetings!!

Code:

#DATA SEGMENT
.data
NUM: .word 1,2,-3,-6,34,-56,5,9,-67,10
count: .word 0
out: .ascii "Number of negative numbers present in the array is "
#CODE SEGMENT
main:
.text
la t0,NUM
li t2,0
li t3,10
li t4,0x80000000
loop:
#PROCESSING
beq t3,zero,end       #if loopcout is 0, then goto end
lw t1,0(t0)       #else load the number
and t1,t1,t4       #check the MSB This is done by Bitwise AND with the number ans 0x80000000
beq t1,zero,positive   #if the result of AND is 0, the number is positivem then goto label positive
addi t2,t2,1       #else the number is negative and count it into the register t2
positive:
addi t0,t0,4       #increment array index
addi t3,t3,-1       #decrement the lopp count
j loop           #repeat
end:
sw t2,count,t0       #store the vakye of count
#DISPLAY MESSAGE
la a0,out       #load the address of the output message
li a7,4           #paraneter for dusplay
ecall           #system call
#DISPLAY THE COUNT
add a0,zero,t2       #load the count into register a0 for display
li a7,1           #parameter
ecall           #system call
li a7,10       #parameter for termmination
ecall           #system call

Output screenshot:Name Number Source zero ra | sp gP 0 1 2 to t1 t2 s0 Text Segment Bkpt Address Code Basic 0x00400000 Ox0fc10297 auipc x5, 0x0

Hope this helps

Thank You

0 0
Add a comment
Know the answer?
Add Answer to:
1. A system with a word length of 32-bit and byte-addressable memory has ten consecutive 32-bit...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Log In

Sign Up

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions

  • Figure below shows part of the byte-addressable program memory that uses big-endien format to store data....

    Figure below shows part of the byte-addressable program memory that uses big-endien format to store data. The memory contains a 32-bit RISC-V instruction at address 0x00408000. Each memory address stores one byte. Derive the exact instruction code stored at address 0x04080000 in the program memory and explain what the assembly instruction does. 7 0 Ox11 0x93 Ox1D Address Ox00408004 Ox00408003 0x00408002 0x00408001 0x00408000 Ox00407FFF Ox00407FFE Ox00407FFD Ox00407FFC Ox87 Ox00 Ox00 Oxld Ox93 Ox01

  • 1. The four-byte sequence 0xA7 0xDB 0xDD 0x72 stored in consecutive memory cells in a little-endian...

    1. The four-byte sequence 0xA7 0xDB 0xDD 0x72 stored in consecutive memory cells in a little-endian architecture represents ___________ (decimal) when interpreted as a 32-bit signed integer. 2. The four-byte sequence 0x8B 0x6A 0x73 0x86 stored in consecutive memory cells in a little-endian architecture represents ___________ (decimal) when interpreted as a 32-bit signed integer. 3. The four-byte sequence 0x22 0x88 0x8A 0x56 stored in consecutive memory cells in a little-endian architecture represents ___________ (decimal) when interpreted as a 32-bit unsigned...

  • A byte-addressable memory system contains four memory modules each of which is 32 bits wide by...

    A byte-addressable memory system contains four memory modules each of which is 32 bits wide by 2^28 cells deep. The system employs a 1 MB 2-way set associative cache with 128-byte cache lines. It also uses a 32-bit CPU-to-memory data bus as well as 32-bit physical addresses. Each memory module requires 4 clock cycles to perform either a read or a write operation. a) Assuming that the memory system is low order interleaved, show the proper 32-bit format for physical...

  • 3. (6 pts) Consider a new processor. The memory system is 32-bit byte- addressable. The on-chip...

    3. (6 pts) Consider a new processor. The memory system is 32-bit byte- addressable. The on-chip cache memory is 128 KByte 4-way set-associative, with a 64 byte block size. (a) Draw a diagram showing how the cache controller will split the memory address: for each field. show its name and number of bits. (b) The design team decided to change the cache architecture to a direct mapped one. For each of the parameters in the following table, indicate the impact...

  • Please answer 2.6.1 2.6 The table below shows 32-bit values of an array stored in memory...

    Please answer 2.6.1 2.6 The table below shows 32-bit values of an array stored in memory Address Data 24 38 2 4 32 36 40 2.6.1 [5] <COD §§22, 2.3-For the memory locations in the table above, write C code to sort the data from lowest to highest, placing the lowest value in the smallest memory location shown in the figure. Assume that the data shown represents the C variable called Array, which is an array of type int, and...

  • 3. Virtual Memory (20 points) An ISA supports an 8 bit, byte-addressable virtual address space. The...

    3. Virtual Memory (20 points) An ISA supports an 8 bit, byte-addressable virtual address space. The corresponding physical memory has only 256 bytes. Each page contains 32 bytes. A simple, one-level translation scheme is used and the page table resides in physical memory. The initial contents of the frames of physical memory are shown below. VALUE address size 8 bit byte addressable each byte of addressing type memory has its own address 32 B page size physical memory size 256...

  • Please write down the solution in detail. 3. (20 pts) Given two 32-bit byte-addressable machines, M1,...

    Please write down the solution in detail. 3. (20 pts) Given two 32-bit byte-addressable machines, M1, and M2, with Mų follow- ing Big Endian and M2 following Small Endian format, it is found that the data Oxabcd1234 (a 32-bit hex number) and Oxffee5678 are returned from the memory when the address 0x00201028 and 0x0020102c are given, respectively, for a read- word operation from both machines. What will you get from memory if you issue a read for (a) a halfword...

  • A certain byte-addressable computer system has 32-bit words, a virtual address space of 4GB, and a...

    A certain byte-addressable computer system has 32-bit words, a virtual address space of 4GB, and a physical address space of 1GB. The page size for this system is 4 KB. Assume each entry in the page table is rounded up to 4 bytes. a) Compute the size of the page table in bytes. b) Assume this virtual memory system is implemented with a 4-way set associative TLB (Translation Lookaside Buffer) with a total of 256 address translations. Compute the size...

  • using the byte memory listed below write out the 32 bit word according to the listed...

    using the byte memory listed below write out the 32 bit word according to the listed format Memory address 00              01.                  02.             03 data. 11001100. 00001000. 11101011. 00110101 1.write the binary word in big Endian Format 2. Write the binary word in little Endian format

  • Consider a virtual memory system with the following properties: 36 bit virtual byte address, 8 KB...

    Consider a virtual memory system with the following properties: 36 bit virtual byte address, 8 KB pages size, and 32 bit physical byte address. Please explain how you determined your answer. a. What is the size of main memory for this system if all addressable frames are used? b. What is the total size of the page table for each process on this processor, assuming that the valid, protection, dirty, and use bits take a total of 4 bits and...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT