Question

Assume the miss rate of an instruction cache is 3% and the miss rate of the data cache is 5%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 120 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 36%. *The size of the tag field-64- (n + m 2). ** The total number of bits in a direct-mapped cache = 2n X (block size + tag size + valid field size) AMATTime for a hit Miss rate X Miss penalty ** Disk Capacity (# bytes/sector) x (avg. # sectors/track) x(# tracks/surface) x (# surfaces/platter) x (# platters!disk) ** Tavg transfer-1/(RPM /( 60 secs/1 min)) x 1/(avg # sectors/track) ** Tavg rotation latency-1/2 x 1/(RPMs / 60 sec/1 min) ** Taccess = Tavg seek + Tavg rotation latency + Tavg transfer

Answer 1

As per the details provided in the question the solution will be as follows:

Given:

Cache miss rate for GCC =3%

Data cache miss rate =5%

CPI_perfect = 2

Miss penalty = 40 cycles

Assumed frequency = 36%

As per the details provided in the question the solution will be as follows: Given: Cache miss rate for GCC = 3% Data cache miss rate = 5% CPI_perfect = 2 Miss penalty = 40 cycles Assumed frequency = 36% Let the Number of insertion = I The Number of memory miss cycles = I times 3% times 120 = I times 0.03 times 120 = 3.6I. Data miss cycles = I times 36% times 5% times 120 = I times 0.36 times 0.05 times 120 = 2.6I Total Number of Memory stall cycles = 3.6I + 2.16I = 5.76 I. The CPI with Memory stall = 2 + 5.76 = 7.76 CPU Time with stalls/CPU Time perfect cache = 1 times CPI_stall times clock cycle/1 times CPI_perfect times clock cycle = CPI_stall/CPI_perfect = 7.76/2 = 3.88 Hope you understand the solution and let me know the doubts in the comments. Have a nice day!!! Please rate...

Hope you understand the solution and let me know the doubts in the comments. Have a nice day!!! Please rate...