Question

Question 3 Shown below is a schematic diagram of a counter made up of three JK flip-flops. (d) Shown below is a master-slave D flip-flop. This is made using two gated D latches. The truth table for a gated D latch is also shown below. HIGH J J CLK ас ас ac Truth table: gated D latch D EN D D, Q. D, 0. 0 0 go CLK ΕΝΟ ENO: 0 0 1 0 1 0 Oo 1 1 1 Complete following timing diagram for the outputs Q and Q. The outputs Q and start low, (4 marks) CLK 1 K к CLR CLR 0 K CLR o HIGH 호 Oo 02 (a) For the CLK input shown below complete the outputs Q Q and Q2. Assume Q Q and Q2 all start LOW (3 marks) CLK D Q11 Qot Q11 01 Q21 (c) The waveform pattern below is required. Devise a ring counter and show how it can be preset to produce this wavefom on its Q, output (On is the MSB). At the 16th Clock pulse the patter begins to repeat (4 marks) (b) What is the modulus of this counter? Is the counter synchronous or asynchronous? (2 marks) Clock LLLLLLLLLLLLLLL 11 12 13 14 15 16 17 18 19 110 111 112 113 114 115 0001101000010101010 09 (c) Show how adding onc gate to this circuit will change its modulus to 6 (ic the counter counts from 0 to 5). Sketch your new circuit. (3 marks)

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Answer 1

9 J J 3 C с Ck si GR CIR Our Qo 12 High Clock elepend on it behave like up Colanter. Output will change when clk is enabled. here and and 3rd JK flip flop Oo Q, (1st and 2nd) JK flip Hop output Qq O, Qo will be. like [000,001, 010,011,100, 101, 110, 111] it is negative triggereal. Sa Ouffet Hill Change only at negative tiggering. dk O € a,

(6) it is Mode Counter, and it is agynchronous Counter becaule Clk depend on on Previous output far Mod-6 conater :- it Will Count 1000-101) When Q2O, Oo will be llo it will reeet. Qq Qq Oo here Q₂ Q, is ll. So take one HAND gate and Output of NARD gate Qan in ar So that llo is repet to 000. . Car is active low) High. J xuk Ulk o Q >ak k CIK k K do PaR CR UR

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