Question

B- If you want to design an 8-bit binary multiplier (A7.Ao) X(B,. Bo). How many AND gates are required. What is the type of Binary adder is required. How many ICs are required of this type?
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Answer 1

In the last section, we saw how to express an 8-bit product as a series of sums of 1-bit products, so-called partial product accumulation. We can exploit the same principle to construct multipliers of wider bit widths using primitive 4-by-4 multiplier blocks. First, we denote the two 8-bit magnitudes to be multiplied as 47-0 and B7-0 and the 16-bit product that results as P15-0. We can partition A and B into two 4-bit groups, A7-4, A3-0, B7-4, B3-0, and form their 16-bit product as a sum of several 8-bit products To see how this works, let's examine the multiplication of the 8-bit binary numbers 111100102 and 100011002. These correspond to the decimal numbers 242 and 140, respectively. 1. 110010 + 1130 011 900 000 101010 1011 000 As a check, we see that 242* 140-33880, which is equal to 10000100010110002. (See Appendix A to review base conversions.)

The hardware implementation follows directly from this observation. It requires four 4-by-4 multipliers, implemented as in Figure 5.31. plus logic to sum the four-bit wide slices of the partial products Let's call the four 8-bit partial products PPO, PP1, PP2, and PP3. Then the final product bits are computed as follows Of course, any carry-out of the calculation of P7-4 must be added to the sum for P11-8, and likewise for the carry-out of P11-8 to P15-1

The basic blocks of the implementation are (1) the calculation of partial products, (2) the summing of the 4-bit product slices, and (3) the carry look-ahead unit. We examine each of these in turn Calculation of Partial Products Each of the S-bit partial products is implemented by a 74284/74285 pair. The subsystem has 16 inputs, the multiplicand and multiplier, and 32 outputs, constituting the four S- bit partial products. The partial product subsystem is shown in Figure 5.31. Calculation of Sums The low-order 4 bits of the final product, P3-0, are the same as PP03-0 and do not participate in the sums. P7-4 and P11-8 are sums of three 4-bit quantities. How do we compute these? Figure 5.32 shows a way to cascade full adders to implement a function that sums three 4-bit quantities, denoted A3-0, B3-0, and C3-0. (Watch that you don't confuse the variable Ci with adder carry-ins.) The first level of full adders sums 1 bit from each of the three numbers to be added. We accomplish this by using the carry input as a data input. The second-level adders combine the carry-out from the next lower order stage with the sum from the first-level adder. The carries simply propagate from right to left among the second-level adders. This is just like the carry propagations we needed in the 4-by-4 multiplier of Figure 5.28.

GA& DA G Figure 533 shows how the logic of Figure 5 32 can be implemented withTT components he first eve fu adders are p от ес У1 133 dual binary adder he second er a dersarem leme ted a 74181 arithmetic ogic unt configured for the adder finction. This has the extra per ormance advantage ofinternal car ν look ahead og Note that the ALU block s written in its positive logic orm, with positive logic data inputs and outputs and negative logic carry-in and carry-out. Figure 5.33 provides the basic building block we can use to implement bit slices P7-4 and P11-8 for the result products. This is shown in Figure 5.34 so. Peures3 The rightmost 74181 component and its two associated 74183s implement bit slice P7-4. The logic is cascaded with an identical block of components to implement bit slice P11-8.

The rightmost 74181 component and its two associated 74183s implement bit slice P7-4. The logic is cascaded with an identical block of components to implement bit slice P11-8 Figure 5.34 also includes the implementation of slice P15-12. The final slice is formed from the partial product PP37-4, plus any carry-outs from lower-order sums. We implement this using a 74181 component configured as an adder, with the B data inputs set to 0, the A inputs set to the partial product, and the carry-in coming from the adjacent adder block. Putting the Pieces Together The last step in the design combines the multiplier block with the accumulation block. To further improve the performance, the carries between the 74181s can be replaced with a 74182 carry look-ahead uni This is shown in Figure 5.35 Arial Toa leribtiom Pe Ps.