Answer : 2 bytes
CMPSW is used to compare words.
It compares a memory operand pointed to by ESI to a memory operand pointed to by EDI.
QUESTION 22 When using CMPSW, the address in edi will be incremented by each interaction. 1...
Question 2 Suppose you have a byte-addressable virtual address memory with 8 virtual pages of 64 bytes each and 4 page frames. Assuming the following page table, Page = Frame Valid Bit 0 0 1 2 3 4 5 What physical address corresponds to the virtual address 0X44 a. OXC1 b.OXC2 COXC4 d. OXCO OXC3
Need help in Question 72
70. With each PULY instruction, the SP is (incremented, decrement- ed) by 71. True or false. We use a section of flash memory for stack. 72. True or false. On power-up, we set the highest address of RAM as the first location of the stack.
Problem #1 (25 points) Address Space, Memory Consider a hypothetical 18-bit processor called HYP18 with all registers, including PC and SP, being 18 bits long. The smallest addressable unit in memory is an 8-bit byte. A. (4 points) What is the size of HYP18's address space in bytes and KB? How many address lines does HYP18 require? Address space: Bytes Address space: KB (KiloBytes). Address bus lines: B. (6 points) Assume that first quarter of the address space is dedicated...
QUESTION 2 Suppose a computer using direct mapped cache has 216 bytes of byte-addressable main memory and a cache of 64 blocks, where each cache block contains 32 bytes. a. How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, (include field names and their sizes) c) To which cache block will the memory address (F8C916 map? What address in that block does it map to?
please answer
$5 UXIF map in the computer uses direct mapping Question 18 5 pts Suppose we have a byte-addressable computer using 2-way set associative mapping with 16-bit main memory addresses and 32 blocks of cache. Suppose also that each block contains 8 bytes. The size of the block offset field is bits, the bits. size of the set field is bits, and the size of the tag field is 5 pts Question 19 Suppose we have a byte-addressable computer...
Question 1 For each of the cache configurations listed below, show the decomposition of a 32 bit address to be used with it. (1 point) a. 1MB direct mapped cache with an 16-byte cache line (2 points) b. 2MB 8-way set associative cache with a 8-byte cache line (2 points) 4MB 32-way set associative cache with a 16-byte cache line (2 points) C.
Question 1 For each of the cache configurations listed below, show the decomposition of a 32 bit...
Compute the effective address and the content of ACC (accumulator) for a load instruction of a 1-address machine for each type of addressing modes using the following assumptions The load instruction is of length 4 bytes, the first byte is for op ode and mode and the other two bytes contain the value 90 for an address or an immediate value ? The load instruction is stored in locations 12-15 The register (say R1)contains the value 800; The location 800...
Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64 bytes each, and 4-page frames. Assuming the following page table, answer the questions below: Page #Frame #Valid Bit0111312-03014215-06-07-0a) How many bits are in a virtual address? b) How many bits are in a physical address? c) What physical address corresponds to the following virtual addresses (if the address causes a page fault, simply indicate this is the case)? 1) Ox00 2) 0x44 3) OxC2 4) 0x80
1) How many bits are needed to address/uniquely identify the LC-3’s eight General Purpose Registers? 2) How many bits or bytes are at each memory location in the LC-3? 3) The minimum and maximum values for an UNSIGNED CHAR (1 byte) are? 4) The minimum and maximum values for a SIGNED CHAR (1 byte) are? 5) The LC-3 has a 16-bit address bus and is able to address up to how many memory locations? Why?/How?/Prove? I don’t want a 2...
3. Virtual Memory (20 points) An ISA supports an 8 bit, byte-addressable virtual address space. The corresponding physical memory has only 256 bytes. Each page contains 32 bytes. A simple, one-level translation scheme is used and the page table resides in physical memory. The initial contents of the frames of physical memory are shown below. VALUE address size 8 bit byte addressable each byte of addressing type memory has its own address 32 B page size physical memory size 256...