Question

I. True/False (Indicate whether the sentence or statement is true or false) (16 points) The number of state variables is 2", where n is the number of bits to encode the states 2. The output of a Mealy machine can change any time, regardless of the elock pulse. 3, The sensitivity #ist for . Mealy and Moore machines should contain the input variables and the clock Usually Mealy machine has less state than Moore machine. The output of a Moore machine is determined by the inputs and current states. VHDL stands for Virtual Hardware Description Language VHDL uses an ENTITY declaration to define the interface of a component or block VHDL uses an ARCHITECTURE declaration to describe how a component or block should perform. 5 8. 2. Multiple Choice (24 points) I. The block of code which defines the relationship between input, output, and internal signals or variables in a VHDL design is the c. package d. library a. architecture b. entity 2. Which VHDL data type can only have a value of'l' or 'o'? a. signal b. std logic c. bit d. integer 3. Which variable name is illegal? a. or2x b. signal c. Vhdl2 d. global_X Which variable name is legal? a. X b. 3inputNor 4. XY-input signal d. Which variable name is illegal? a. Xunder b. Xsignal c. Xsignal d. x9signal A finite state machine has an output determined only by the present state of the system is Moore machine Mealy machine c. Max machine d. Minimum machine

Answer the following questions

Answer 1

1)

1. True

n is number of bits and we can hace 2ⁿ states. e.g, for n =2 , we have 2 to 4 encoder.

2. True.

The Mealy output can change anytime regardless of clock.

3. False.

The sensitivity list should have only clk as ouput changes instantly when input changes.

4. True

Mealy has Different outputs on arcs (n^2) rather than states (n)

5. False

The output is determined by current state only.

6. False

It stands Very High Speed Integrated Circuit Hardware Description Language.

7. True

Entity is used to declare all inputs and output pins of the block. So, as a block has input and output as interface. So, VHDL uses entity to define interface of block or component.

8. True.

Yes VHDL uses architecture declartion to describe how the component or block should perform. As architecture has all the information of what logic is to be performed.

Please 1 question at a time with maximum 4 sub parts. Although I had answered all 8. Please rate and post 2 nd question again