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Finite State Machine Diagram, Datapath and Controller. Give a complete RTL design (the three components just...

Finite State Machine Diagram, Datapath and Controller. Give a complete RTL design (the three components just mentioned) for a system that divides two 8-bit unsigned integers, x and y, using the division by subtraction algorithm (you may need to look this up). The circuit should have two 8-bit outputs, the quotient q, and the remainder, r.
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Answer #1

Remainder computation algorithm invokes additional elements in the datapath: Arithmetic
Logic Unit (ALU) and up/down counter. ALU is, in a sense, a custom block, its
functionality is design specific. For this particular algorithm ALU should handle addition,
subtraction and right/left shift operations, as well as comparison.
The complete block scheme below Figure.

The control unit gets feedback from datapath via six (X6-X1) signals. X1 indicates whether

the content of RG1 equals the content of RG2. X2 signals whether the value stored in RG1

is greater than the value of RG2. X3 is the most significant bit of RG2. X4 is the sign bit of

RG1. Signals X5 and X6 indicate when content of counter and RG1 equal zero.The Datapath of GCD circuit below figure.

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