Design the following finite state machine (FSM). It has two 1-bit inputs (in1 and in2) and...
Design the following finite state machine (FSM). It has two 1-bit inputs (in1 and in2) and two 1-bit outputs (out1 and out2). The first output (out1) bit should be equal to one if, on both of the last two cycles, in1 and in2 were EQUAL to each other; otherwise, out1 should equal zero. The second output (out2) should be equal to 1 if, on the last cycle, in1 and in2 were NOT EQUAL to each other; otherwise, out2 should equal zero.
Draw a state transition diagram where each state has a unique name that is a string of bits (eg, 00, 01, and 11). Write the associated output and label all the arcs between transitions with the inputs causing them. This must be a Moore machine.
Draw a truth table with both inputs, the current state bits, the outputs, and the next state bits.
Homework Answers
State Table
|
STATE |
PRESENT STATE |
INPUTs |
NEXT STATE |
OUTPUTs |
||||
|
Q1 |
Q0 |
In2 |
In1 |
Q1+ |
Q0+ |
Out2 |
Out1 |
|
|
S0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
|
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
|
|
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
|
|
0 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
|
|
S1 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
|
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
|
|
0 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
|
|
0 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
|
|
S2 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
|
1 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
|
|
1 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
|
|
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
|
|
S3 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
|
1 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
|
|
1 |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
|
|
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
|
NextState and Output expressions:
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