Question

A new version of the MIPS architecture called(called MIPS2) uses cache memories that consume two clock cycles but the access is pipelined. The four instruction classes ALU, LOAD, STORE, and CONTROL have frequencies of 40%,20%,15% and 25% resp.

a) How many pipeline stages has the new MIPS2. Draw the pipeline structure.

b) Assuming the forwarding technique is used, determine the data hazards and compute the stall penalties.

c) Assuming branch conditions and the target addresses are computed in the decode stage, determine control hazards and compute the stall penalties.

d) compute the average cpi of MIPS2.

Answer 1