Explain your answer.
True or False:
If physical memory is 16MB, then the page table for process B has at most 256 entries if each page is 512KB.
If the memory is byte addressable.
Total frames available with 16mb physical memory =physical memory /frame size(which is equal to page size).
=224/219
=25=32. So totally 32 frames are available, in worst case, all the frames will be occupied by process B. Which means 32 pages are the almost size of process B.
So page table at most contains 32 entries.
--------------So given statement is "false" - - - - - - - - - - -
Explain your answer. True or False: If physical memory is 16MB, then the page table for...
Suppose a memory manager employs paging with page size of 4 Kbytes. It has a memory of 256 Mbytes. A process of size 25 Kbytes needs to be loaded into memory. Answer the following. (a) How many frames are there in the memory? (b) How many bits are necessary to represent the physical address as <frame#, offset>? (c) How many frames need to be allocated to the process?
Suppose a memory manager employs paging with page size of 4 Kbytes....
3. Virtual Memory (20 points) An ISA supports an 8 bit, byte-addressable virtual address space. The corresponding physical memory has only 256 bytes. Each page contains 32 bytes. A simple, one-level translation scheme is used and the page table resides in physical memory. The initial contents of the frames of physical memory are shown below. VALUE address size 8 bit byte addressable each byte of addressing type memory has its own address 32 B page size physical memory size 256...
Assume that the following section of main memory is used to store the page table for 3 different processes. The page-table base register values for process P1 is 1080, for P2 is 1085, and for P3 is 1090. Assume that the contests of memory below correspond to frame numbers. Also assume that frame size is 4096 contents 3584720 15 11 18 6 20 24 910 13 30 38 40 1 addresses 0 0 0 0 0 O 000 0 00...
A computer uses a byte-addressable virtual memory system with a four-entry TLB and a page table for a process P. Pages are 16 bytes in size. Main memory contains 8 frames and the page table contains 16 entries. a. How many bits are required for a virtual address? b. How many bits are required for a physical address?
Computer
architecture
Question 25 Answer the following about the memory system with virtual memory. Select True/False (T/F) for each statement. It's possible to get: TLB hit/Cache miss. (Select] T It's possible to get: TLB miss/Page Table hit/Cache hit ( Select ] F It's possible to get: TLB miss/Page Table hit/Cache miss. [Select ] It's possible to get: TLB miss/Page Fault/Cache hit. (Select]
Suppose we have 212 bytes of virtual memory and 27 bytes of physical main memory. Suppose the page size is 24 bytes. a) How many pages are there in virtual memory? b) How many page frames are there in main memory? c) How many entries are in the page table for a process that uses all of virtual memory?
Suppose we have 2^20 bytes of virtual memory and 216 bytes of physical main memory. Suppose the page size is 2^8 bytes. a) How many pages are there in virtual memory? b) How many page frames are there in main memory? c) How many entries are in the page table for a process that uses all of virtual memory?
Number Name 3. Assuming no page fault on a page table access, what is the processor memory access time for the system depicted in the above figure, for a physical memory with 50ns read/write times? 4. Now, assume that the memory system has a translation look-aside buffer (TLB). The TLB requires 10 ns to determine a hit or mess. The physical memory system has an access time of 50ns. You may assume that page fault rate for the application is...
page tables for large processes can easily take up a large amount of physical memory. one, proposed, solution to this problem is to use a multilevel page map table and put some portions in virtual memory. Explain how you would implement that. In your answer, please, specifically, discuss how a virtual address would be converted to a physical address.
Consider a simple paging system with the following parameters: 232 bytes of physical memory; page size of 210 bytes; 216 pages of logical address space. How many entries in the page table? How many bits in each page table entry? Assume each page table entry contains a valid/invalid bit.