Question

Design using VHDL a 5 input majority voter circuit that outputs a 1 when majority of inputs are 1. inputs can be named A, B , C , D, E. Design using if and else wherever possible.

Answer 1

entity vhd_majority is

port(A: in std_logic_vector (4 downto 0);

Y out std_logic);

end vhd_majority;

architecture behavioral of vhd_majority is

begin

process(A)

variable temp:=0;

begin

for i in 0 to 4 loop

if (A(i)=='1') then

temp=temp+1;

endif;

end loop

if(temp>2) then

y<= 1;

else

y<=0;

endif ;

end process;

end behavioral