Write a behavioral code in VHDL for a 3 - input majority circuit. This means that...
Write a behavioral code in VHDL for a 3 - input majority circuit. This means that if the majority of inputs is 1, the output is 1. Otherwise, the output is 0.
Homework Answers
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity majority1 is
Port ( I : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC);
end majority1;
architecture Behavioral of majority1 is
begin
process (I)
begin
if (I <= "000") then
Y <= ‘0’;
elsif (I <= "001") then
Y <= ‘0’;
elsif (I <= "010") then
Y <= ‘0’;
elsif (I <= "011") then
Y <= ‘1’;
elsif (I <= "100") then
Y <= ‘0’;
elsif (I <= "101") then
Y <= ‘1’;
elsif (I <= "110") then
Y <= ‘1’;
else (I <= "111") then
Y <= ‘1’;
end if;
end process;
end Behavioral;
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