Question

Fibonacci: case. Write a VHDL description for a circuit that accepts a four-bit input and outputs true if the input is a Fibonacci number (0, 1, 2, 3, 5, 8, or 13). Your implementation must be done via a case statement.

Answer 1

ANSWER(main module along with test bench)

/*
* Do not change Module name
*/
module mod(in1,out);
input[3:0] in1;
output reg out;

always@(in1)
begin

case(in1)
0,1,2,3,5,8,13: out<=1;
default: out<=0;
endcase
end
  
endmodule

module tb;
reg[3:0] rin1;
wire wout;

mod m1(rin1,wout);

initial
begin
rin1=4'd0;
#4 $display("output=%b when input 0",wout);
rin1=4'd1;
#4 $display("output=%b when input 1",wout);
rin1=4'd2;
#4 $display("output=%b when input 2",wout);
rin1=4'd3;
#4 $display("output=%b when input 3",wout);
rin1=4'd5;
#4 $display("output=%b when input 5",wout);
rin1=4'd8;
#4 $display("output=%b when input 8",wout);
rin1=4'd13;
#4 $display("output=%b when input 13",wout);
rin1=4'd12;
#4 $display("output=%b when input 12",wout);
end

endmodule

OUTPUT:

module mod(ini, out); input[3:0] inn; output reg out; output=1 when input o output=1 when input 1 output=1 when input 2 output=1 when input 3 output=1 when input 5 output=1 when input 8 output=1 when input 13 output=0 when input 12 always@(in1) begin case(ini) 0,1,2,3,5,8,13: out<=1; default: out<=; endcase end endmodule module tb; reg[3:0] rini; wire wout; mod m1(rini, wout); initial begin rin1=4'de; #4 $display("output=%b when input 8", wout); rin1=4'd1; #4 $display("output=%b when input 1", wout); rin1=4'd2; #4 $display("output-%b when input 2", wout); rin1=4'd3; #4 $display("output=%b when input 3", wout); rin1=4'd5;