Question

virtual memory support into our baseline 5-stage MIPS pipeline using the TLB miss handler. Assume that accessing the TLB does not incur an extra cycle in memory access in case of hits.
Without virtual memory support (i.e. she had only a single address space for the entire system, or a physical address is same as a logical address), the average cycles per instruction (CPI) was 2 to run Program X. If the TLB misses 10 times for instructions and 20 times for data in every 1,000 instructions on average, and it takes 400 cycles to handle a TLB miss, what will be the new CPI?

Answer 1

CPI = CPIbase + Penalty

Penalty = TLB miss penalty cycle per instruction

       = TLB miss per instruction * penalty cycle per TLB miss

Here CPIbase is 2

TLB miss of 1000 instruction for instruction=10

TLB miss of 1000 instruction for data=20

so,TLB miss per instruction for instructions=10/1000

so,TLB miss per instruction for data=20/1000

and penanlty cycle per miss =400 cycles

now apply the above formula for both data and instruction

therefore,

=2+(10/1000+20/1000)*400

=2+(30/1000)*400

=2+12

=14 (answer)