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Exercise 8.16 You are building a computer with a hierarchical memory systenm that consists of separate instruction and data caches followed by main memory. You are using the ARM multicycle processor from Figure 7.30 running at 1 GHz (a) Suppose the instruction cache is perfect (i.e., always hits) but the data cache has a 5% miss rate. On a cache miss, the processor stalls for 60 ns to access main memory, then resumes normal operation. Taking cache misses into account, what is the average memory access time? How many clock cycles per instruction (CPI) on average are required for load and store word instructions considering the non-ideal memory system? (b) Consider the benchmark application of Example 7.5 that has 25% loads, 10% stores, 13% branches, and 52% data-processing instructions. Taking the non-ideal memory system into account, what is the average CPI for this benchmark? (c) (d) Now suppose that the instruction cache is also non-ideal and has a 7% miss rate. What is the average CPI for the benchmark in part (c)? Take into account both instruction and data cache misses
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In the heirarchical model the memory consists of separate instruction and data caches along with main memory. This ARM processor is running at 1GHz.

a) Given,

The instruction cache is always hit where as the data cache is 5% miss.

The processor takes 60ns to access main memory

Average memory access time is given as;

T = 1 + 0.05 * 60

T = 4 ns

b) For the non - ideal memory system , the average CPI required to store and load word instruction is;

CPI = ( 5 * 25 + 4 * 10 ) / 100

CPI = 1.65

4 cycles for store instructions and 5 cycles for load instructions.

c) The average CPI for the benchmarkis,

ACPI = (5*25 + 4*10 + 3*11 + 3*2 + 4*52)/100

ACPI = 4.12

d) Now for 7 % miss rate the average CPI is given as,

ACPI = 4.12 + 2.45

ACPI = 6.57

( 25+10 = 35 are load and store instructions * 0.07 = 2.45 )

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