Consider a processor with a CPI of 1.5, excluding memory stalls. The instruction cache has a...
1. Consider a program that can execute with no stalls and a CPI of 1 if the underlying processor can somehow magically service every load instruction with a 1-cycle L1 cache hit. In practice, 5% of all load instructions suffer from an L1 cache miss, 2% of all load instructions suffer from an L2 cache miss, and 1% of all load instructions suffer from an L3 cache miss (and are serviced by the memory system). An L1 cache miss stalls...
Exercise 8.16 You are building a computer with a hierarchical memory systenm that consists of separate instruction and data caches followed by main memory. You are using the ARM multicycle processor from Figure 7.30 running at 1 GHz (a) Suppose the instruction cache is perfect (i.e., always hits) but the data cache has a 5% miss rate. On a cache miss, the processor stalls for 60 ns to access main memory, then resumes normal operation. Taking cache misses into account,...
4B, 20%) compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI1 Assume main memory access time of 8 cycles Assume 40% instructions require memory data access Assume cache access time of I cycle Assume hit rate 0.90 for instructiens, 0.80 for data Assume miss penalty (time to read memory inte cache and from cache to Processor with cache processor) is 10 cycles >Compare execution times of 100-thousand instructions: 4B,...
For gcc, the frequency for all loads and stores is 36%. Instruction cache miss rate is 5%. Data cache miss rate is 10%. If a machine has a CPI of 2 without memory stalls and the miss penalty is 40 cycles for all misses, how much faster is a machine with a perfect cache? increase the performance by doubling its clock rate. Since the main memory speed is unlikely to change, assume that the absolute time to handle a cache...
Assume the miss rate of an instruction cache is 3% and the miss rate of the data cache is 5%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 120 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 36%. *The size of the tag field-64- (n + m 2). ** The total...
6. Memory Access Time [15 points] Consider a MIPS processor that includes a cache, a main memory, and a hard drive. Access times of cache memory, main memory, and hard drive are 5 ns, 200 ns, and 1000 ns, respectively. Assume that cache memory is divided into instruction cache and data cache. Assume that data cache has a 90% hit rate. Assume that main memory has a 98% hit rate and hard drive is perfect (it has a 100% hit...
Assume an memory hierarchy with unified data and instruction memories, miss rate equal to 15%, miss penalty equal to 90 cycles, 25% Load/Store instructions, TLB miss ratio per TLB access equal to 6% and TLB miss penalty equal to 80 cycles. What is the realistic CPI of this system if the ideal CPI is 1.5? What is the speedup compared to not having TLB? What would be the speedup if the TLB could hold every entry?
Base machine has a 2.4GHz clock rate. There is L1 and L2 cache. L1 cache is 256K, direct mapped write through. 90% (read) hit rate without penalty, miss penalty is 4 cycles. (cost of reading L2) All writes take 1 cycle. L2 cache is 2MB, 4 way set associative write back. 95% hit rate, 60 cycle miss penalty (cost of reading memory). 30% of all instructions are reads, 10% writes. All instructions take 1 cycle - except reads which take...
1. Cache memory (8pts) Consider adding cache to a processor-memory system design. The microprocessor without cache needs 12 clock cycles to read a 16-bit word from the memory. With cache, it takes only 4 clock cycles if the data happens to be in the cache and a total 20 clock cycles including the cache misses. a. What is the performance ratio of the cache system to the non-cache system given a hit rate of 80%? b. For what hit rate...
1. Cache memory (8pts) Consider adding cache to a processor-memory system desigrn. The microprocessor without cache needs 12 clock cycles to read a 16-bit word from the memory. With cache, it takes only 4 clock cycles if the data happens to be in the cache and a total 20 clock cycles including the cache misses a. What is the performance ratio of the cache system to the non-cache system given a hit rate of 80%? b. For what hit rate...