1. Consider a program that can execute with no stalls and a CPI of 1 if...
Consider a processor with a CPI of 1.5, excluding memory stalls. The instruction cache has a miss rate of 1.5%, whereas the miss rate of the data cache is 3.5%. The miss penalty of the data cache is 80 cycles. The percentage of load/store instructions within the running programs is 25%. If the CPI of the whole system, including memory stalls, is 2.5, calculate the miss penalty of the instruction cache. Miss penalty of the instruction cache- Cycles.
Systems Programming problem: Consider a processor with the following parameters Base CPI (no Memory Stall) Clock rate L1 miss rate L2 Direct Mapped speed L2 Direct Mapped miss rate L2 8-way set associative speed L2 8-way set associative miss rate 1. 1.5 2 GHz 12 cycles 3.5% 28 cycles 1.5% Main Memory Access Time = 50 ns Calculate the CPI with L1 only * Calculate the CPl with L1 and L2 Direct Mapped Calculate the CPI with L1 and L2...
A short program loop goes through a 16 kB array one word at a time, reads a number from the array, adds a random number, and stores the result in the corresponding entry in another array that is located in the memory immediately following the first array. An outer loop repeats the above operation 100 times. The 64-bit processor, operating at a clock frequency of 4 GHz, is pipelined, has 48 address lines, three levels of caches with a 64...
Exercise 8.16 You are building a computer with a hierarchical memory systenm that consists of separate instruction and data caches followed by main memory. You are using the ARM multicycle processor from Figure 7.30 running at 1 GHz (a) Suppose the instruction cache is perfect (i.e., always hits) but the data cache has a 5% miss rate. On a cache miss, the processor stalls for 60 ns to access main memory, then resumes normal operation. Taking cache misses into account,...
Base machine has a 2.4GHz clock rate. There is L1 and L2 cache. L1 cache is 256K, direct mapped write through. 90% (read) hit rate without penalty, miss penalty is 4 cycles. (cost of reading L2) All writes take 1 cycle. L2 cache is 2MB, 4 way set associative write back. 95% hit rate, 60 cycle miss penalty (cost of reading memory). 30% of all instructions are reads, 10% writes. All instructions take 1 cycle - except reads which take...
2. Cache hierarchy You are building a computer system with in-order execution that runs at 1 GHz and has a CPI of 1, with no memory accesses. The memory system is a split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32 KB each, with a block size of 64 bytes. The memory system is split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32 KB each, with a block...
a) Calculate the AMAT for a cache system with one level of cache between the CPU and Main Memory. Assume that the cache has a hit time of 1 cycle and a miss rate of 11%. Assume that the main memory requires 300 cycles to access (this is the hit time) and that all instructions and data can be found in the main memory (there are no misses). b) Let us modify the cache system from part (a) and add...
A program (or a program task) takes 150 million instructions to execute on a processor running at 2.7 GHz. Suppose that 50% of the instructions execute in 3 clock cycles, 30% execute in 4 clock cycles, and 20% execute in 5 clock cycles. What is the execution time for the program or task? Suppose the processor in the previous question part is redesigned so that all instructions that initially executed in 5 cycles and all instructions executed in 4 cycles...
4B, 20%) compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI1 Assume main memory access time of 8 cycles Assume 40% instructions require memory data access Assume cache access time of I cycle Assume hit rate 0.90 for instructiens, 0.80 for data Assume miss penalty (time to read memory inte cache and from cache to Processor with cache processor) is 10 cycles >Compare execution times of 100-thousand instructions: 4B,...
Suppose a program (or a program task) takes 1 billion instructions to execute on a processor running at 2 GHz. Suppose also that 50% of the instructions execute in 3 clock cycles, 30% execute in 4 clock cycles, and 20% execute in 5 clock cycles. What is the execution time for the program or task?