Question

Table 1:

Load	26%	Compare	14%	Shift left and shift right	4%
Store	9%	Load immediate	4%	AND	3%
Add	14%	Conditional branch	17%	OR	5%
Sub	0%	Jump	1%	Other register-register instructions (XOR, NOT, etc.)	1%
Multiply	0%	Call	1%
Divide	0%	Return	1%

Using the data in Table 1, which of the following two enhancements will result in faster execution of the five benchmark programs that are described by the instruction frequency data? Assume that the computer used to gather the instruction frequency data in Table 1 had no cache memory and used main memory for all fetch and store memory accesses.
    Enhancement 1: Buy a faster, more expensive processor. The time to complete the Fetch-Execute cycle for every instruction except those accessing a memory address is reduced by 10% by using faster, higher-priced MOSFET transistors for the processor circuit.
   Enhancement 2: Buy faster, more expensive DRAM memory. The average access time for data accesses only is reduced by one third and is the same for either fetch or store access.
Hint: When reduction in time is given for an enhancement, that datum must be converted to a speedup for the enhancement before the conventional formulation of Amdahl’s Law can be employed to compute overall speedup.

Answer 1

Given that

we have to  Using the data in Table 1, which of the following two enhancements will result in faster execution of the five benchmark programs that are described by the instruction frequency data? Assume that the computer used to gather the instruction frequency data in Table 1 had no cache memory and used main memory for all fetch and store memory accesses.

ALU register-register	add, sub, multiply, divide, shift left and shift right, AND, OR, Other register-register (xor, not, etc.)
Memory access	load, store, load immediate
Conditional branch	conditional branch,
Jump	call, return, jump