Question

1. Introduced by IBM with its System/360, the _________ is a set of computers offered with different price and performance characteristics that presents the same architecture to the user.

2. A large number of general-purpose registers, and/or the use of compiler technology to optimize register usage, a limited and simple instruction set, and an emphasis on optimizing the instruction pipeline are all key elements of _________ architectures.

3. The difference between the operations provided in high-level languages (HLLs) and those provided in computer architecture is known as the ________.

4. Blocks of memory, recently used global variables, memory addressing, and one operand addressed and accessed per cycle are characteristics of _________ organizations.

5. Individual variables, compiler assigned global variables, register addressing, and multiple operands addressed and accessed in one cycle are characteristics of __________ organizations.

6. The acronym RISC stands for __________.

7. Although a variety of different approaches to reduced instruction set architecture have been taken, certain characteristics are common to all of them: register-to-register operations, simple addressing modes, simple instruction formats, and __________.

8. A ________ is defined to be the time it takes to fetch two operands from registers, perform an ALU operation, and store the result in a register.

9. The acronym CISC stands for _________.

10. __________ is a way of increasing the efficiency of the pipeline by making use of a branch that does not take effect until after execution of the following instruction.

11. ________ can improve performance by reducing loop overhead, increasing instruction parallelism by improving pipeline performance, and improving register, data cache, or TLB locality.

12. The MIPS R4000 processor chip is partitioned into two sections, one containing the CPU and the other containing a _________ for memory management.

13. A ________ architecture replicates each of the pipeline stages so that two or more instructions at the same stage of the pipeline can be processed simultaneously.

14. The acronym SPARC stands for __________.

15. The work that has been done on assessing merits of the RISC approach can be grouped into two categories: quantitative and _________.

Answer 1

1 .Family concept

2. RISC architectures

3. Semantic gap.

4.cache organizations

5.large register file organizations

6.Reduced Instruction set Computer

7. One instruction per cycle

8.Machine cycle

9. Complex instruction set Computer

10. Delayed branch

11.Unrolling

12. Coprocessor

13.Superscalar architecture

14. SPARC- Scalable Processor Architecture

15.Qualitative.

13.

14.

15.