Question

[13 pts] Complete the timing chart, below, for a D latch with enable (C), and answer the questions that follow. Assume each gate has 10 ns of delay (tPLH and tPHL), and that each division on the chart is 10 ns QN XN DN IN RN (a) Determine the minimum time input C should be asserted (while the D input remains stable) to ensure reliable operation of the latch (b) Determine the nominal setup time provided for the D latch (c) Determine the nominal hold time provided for the D latch (e) Determine the tpHL(D-a) of the D latch

Answer 1

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