Question

2. (a) Name and give a short description of the four design styles for describing a logic function in an architecture? (b) List three concurrent signal assignment statements (c) The following two VHDL codes (architecture part) desanbe the logic diagram shown in Fig 1 (c) using different design styles. Discuss in detail the design style used for each description. begin My-Proc process (DOD 02 architecture architecture 1 of Entity 1 is Signal or out:std logie begin begin (IDO or D1 and D2)1 hen or out DO or D1: D ot end E end prooess My Proc D-out 。= or-out and D2: end anchidecture 1 DO D1 out D2 Fig 1(c). Logic diagram 3. (a) A process in a behavioural design style contains a list of signals. Name this list and briefly explain its use. (c) What type of statements are used within a process? (d) The entity declaration of the logic diagram shown in Fig 3(dX1) is given in Fig. 3(dX2). Write three different VHDL codes to describe the architecture body using: 0 A structural design style (i) A behavioural design style. () A dataflow design style. XOR3 ent is orz, out AB,CD: in std logic ord out Fig. 3(d1) Logic diagram Fig. 3(d)2) Entity declaration

Answer 1

(a)

Four design styles are:

1. Data Flow    : The flow of data through input to output is expressed using concurrent statements
2. Behavioral   : The behavior of input to output is expressed using sequential statements. It’s a highest level of abstraction.
3. Structural    : An entity is described as a set of interconnected components. Component instances are concurrent in behavior.
4. Hybrid          : A hybrid description includes all above styles i.e. data flow, behavioral and structural.

(b)

1. Block statement
2. process statement
3. concurrent signal assignment statement

(c)

Architecture 1 : It’s a data flow design style. Here D_out is the output port related to D0, D1 and D2.

Architecture 2 : It’s a behavioral description styles. Here there is absence of description regarding implementation.

3 (a) It is called sensitivity list of process. Process body is sensitive to these list of signal. Any event occurring on these signal will cause execution of sequential statements in process body.

(c) Sequential statements are used in process body

(d)

(i)

architecture structural_arch of XOR3 is

component XOR2 is

               port (     X, Y        : in std_logic;

                              Z             : out std_logic

               );

end XOR2;

signal xor1_out, xor2_out, xor3_out: std_logic;

begin

uut0: XOR2 port map (A, B, xor1_out);

uut1: XOR2 port map (xor1_out, C, xor2_out);

uut2: XOR2 port map (xor2_out, D, xor3_out);

end arch;

(ii)

architecture behavioral_arch of XOR3 is

begin

process (A, B, C, D)

begin

               if (A = ‘0’ and B=’0’ and C=’0’ and D=’0’) then xor3_out <= ‘0’;

               elsif (A = ‘0’ and B=’0’ and C=’0’ and D=’1’) then xor3_out <= ‘1’;

               elsif (A = ‘0’ and B=’0’ and C=’1’ and D=’0’) then xor3_out <= ‘1’;

               elsif (A = ‘0’ and B=’0’ and C=’1’ and D=’1’) then xor3_out <= ‘0’;

               elsif (A = ‘0’ and B=’1’ and C=’0’ and D=’0’) then xor3_out <= ‘1’;

               elsif (A = ‘0’ and B=’1’ and C=’0’ and D=’1’) then xor3_out <= ‘0’;

               elsif (A = ‘0’ and B=’1’ and C=’1’ and D=’0’) then xor3_out <= ‘0’;

               elsif (A = ‘0’ and B=’1’ and C=’1’ and D=’1’) then xor3_out <= ‘1’;

               elsif (A = ‘1’ and B=’0’ and C=’0’ and D=’0’) then xor3_out <= ‘1’;

               elsif (A = ‘1’ and B=’0’ and C=’0’ and D=’1’) then xor3_out <= ‘0’;

               elsif (A = ‘1’ and B=’0’ and C=’1’ and D=’0’) then xor3_out <= ‘0’;

               elsif (A = ‘1’ and B=’0’ and C=’1’ and D=’1’) then xor3_out <= ‘1’;

               elsif (A = ‘1’ and B=’1’ and C=’0’ and D=’0’) then xor3_out <= ‘0’;

               elsif (A = ‘1’ and B=’1’ and C=’0’ and D=’1’) then xor3_out <= ‘1’;

               elsif (A = ‘1’ and B=’1’ and C=’1’ and D=’0’) then xor3_out <= ‘1’;

               elsif (A = ‘1’ and B=’1’ and C=’1’ and D=’1’) then xor3_out <= ‘0’;

               end if;

end process;

end behavioral_arch;

(iii)

architecture dataflow_arch of XOR3 is

begin

xor2_out <= A xor B xor C xor D;

end dataflow_arch;