Question

ušing a generate l Denavioral module Vr8to256decb for the same icatin te a test bench Vr8to256dec.tb2 that compares the der d

6.27 using verilog

outputs of the two decuucis a Verilog module Vrmultidec8 for a customized decoder that has the ction table in Table X6.27. Us

ušing a generate l Denavioral module Vr8to256decb for the same icatin te a test bench Vr8to256dec.tb2 that compares the der deco outpu quliputs o aierilos module Vrmultidec8 for a customized decoder that has the the two decoders. mpares a Verilog n Design Table X6.27. Use a coding style that is easy to write and check t results atches eaction he function table. agains iplexer output CS L A2 A1 Output to Assert none BILL MARY JOAN PAUL ANNA FRED 0 ing of uts, it alues, more 0 Table X6.27 ATIF KATE 3 Write another function table for the customized decoder in Table X6.27, one that here GS L isQ(n don't-care inputs), In the last colum. ts of Winte another function table includes all eicht rous w e fit
outputs of the two decuucis a Verilog module Vrmultidec8 for a customized decoder that has the ction table in Table X6.27. Use a coding style that is easy to write and check against the function table. CSL A2 A1 A0 Output to Assert none BILL MARY JOAN PAUL ANNA FRED ATIF KATE 0 Table X6.27
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Answer #1
module Vrmultidec8(
    input [2:0] A,
    input CS_L,
    output [8*4,1] output
);

reg [8*4, 0] output;

always @(CS_L)
begin
    if(CS_L) begin
        if(A[2] == 1'b0 && A[1] == 1'b0) begin
            output <= "BILL";
        end else if (A[2] == 1'b0 && A[0] == 1'b0) begin
            output <= "MARY";
        end else if (A[2] == 1'b0 && A[1] == 1'b1) begin
            output <= "JOAN";
        end else if (A[2] == 1'b0 && A[0] == 1'b1) begin
            output <= "PAUL";
        end else if (A[2] == 1'b1 && A[1] == 1'b0) begin
            output <= "ANNA";
        end else if (A[2] == 1'b1 && A[0] == 1'b0) begin
            output <= "FRED";
        end else if (A[2] == 1'b0 && A[1] == 1'b1) begin
           output <= "ATIF";
        end else if (A[1] == 1'b1 && A[0] == 1'b1) begin
           output <= "KATE";
        end
    end
end

endmodule

The module has 2 inputs:

1. A with 3 bits

2. CS_L with 1 bit

The output has 32 bits. This is because there are 4 characters in the output and each character is of 8 bits.

So the size of output = 8*4 = 32;

We are using bit extraction of register to compare with values in table.

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