Consider a hypothetical computer with an instruction set of only two n-but instructions. The firs...
Consider a hypothetical computer with an instruction set of only two n-bit instruc- tions.The first bit specifies the opcode, and the remaining bits specify one of the 2-1 n-bit words of main memory. The two instructions are as follows: 12.7 SUBS X Subtract the contents of location X from the accumulator, and store the result in location X and the accumulator. Place address X in the program counter JUMPX A word in main memory may contain either an instruction or...
5) True or False. HALT is actually a TRAP instruction. Using operate type instructions only place the value 45 in RI . 6) 7) True or False. In a Von Neumann machine data and instructions both reside in memory. What is the opcode for GETC in LC-3. 8) (i)True or False. In LC-3 all memory can be accessed with 16 bits. G) Give the decimal value for this 2's complement bit pattern: 111111110001 (k) Give the decimal number 119 as...
Suppose a computer has 20-bit instructions. The instruction set consists of 32 different operations. All instructions have an opcode and two address fields (allowing for two addresses). The frst of these addresses must be a register, and the second must be memory. Expanding opcodes are not used. The machine has 16 registers. What is the maximum allowable size for memory? o 2 K byte O 14K byte O 11 K byte Next » ous Suppose a computer has 20-bit instructions....
pls both ans Question 20 5 pts Suppose a computer has 32-bit instructions. The instruction set consists of 64 different operations. All instructions have an opcode and two address fields (allowing for two addresses). The first of these addresses must be a register direct address, and the second must be a memory address. Expanding opcodes are not used. The machine has 16 registers. How many bits can be used for the memory address? Question 21 5 pts Suppose we have...
[20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment" of the form STA (x)- : M(M(x)) ← AC, M(x) ← M(x)+1 Suppose we want to implement this instruction on the pseudo-CPU discussed in class augmented with a temporary register TEMP. An instruction consists of 16 bits: A 4-bit opcode and a 12-bit address. All operands are 16 bits. PC and MAR each contain 12 bits. AC, MDR, and TEMP each contain 16 bits,...
Question 20 5 pts Suppose a computer has 32-bit instructions. The instruction set consists of 64 different operations. All instructions have an opcode and two address fields (allowing for two addresses). The first of these addresses must be a register direct address, and the second must be a memory address. Expanding opcodes are not used. The machine has 16 registers. What's the size of the largest memory space that can be addressed by this computer?Assume byte addressable memory.
The AVR provides a rich instruction set to support high-level languages. The AVR address- ing modes also simplify the access of complex data structures. The AVR has a version of the ADD instruction that includes the C flag as one of the source operands, which enables multiple- precision addition operation. The AVR also has a version of the SUB instruction that includes the C flag as one of source operands and hence is used to perform multiprecision subtraction operation. The...
1.) a.) Using the simplified instruction set shown for part b, write code for the following. Suppose memory locations 1400 to 1449 contain 16-bit words. Each word represents 2 ASCII characters. Write code to read in and write out these 100 characters. Left-side character from location 1400 should be first, right-side character from location 1400 should be second, and remaining characters follow in numeric order. Assume you have access to 4 registers: R1, R2, R3, R4. Each register holds one...
Instruction set architecture R: register X, Y, Op1, Op2: Operand Quantity: constant value EA: Effective memory address Opcode Operation Name MOV X Y XCH Opl, Op2 ADD X, Y SUB X, Y SAL Op. Quantity SAR Op. Quantity SHR Op Quantity AND X, Y OR X. Y XOR X, Y NOT X LOAD RA LOAD R. (A) STORERA STORE R. (A) Description Move data from Y to X Exchange Opl with Op2 X=X+Y X=Y-X Shift Arithmetic Left on Op for...
26. The is a group of bits that tells the computer to perform a specific operation A). program counter B). Opcode C). register D). microoperation 27. A condition called occurs in unsigned binary representation of a number when the result of an arithmetic operation is outside the range of allowable precision for the given number of bits. A). underflow B). 2's complement C). overflow D) bitwise complement 28. An iteration of the fetch-decode-execute cycle includes which of the following events?...