Question

by using VIVADO , design 16 bit adder ( code + Testbench)

- half adder

- full adder using half adder

- 4 bit adder using full adder

-16 bit adder using 4 bit adder

Answer 1

Half Adder :

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity half_adder is
port (
input1 : in std_logic;
input2 : in std_logic;
--
sum_out : out std_logic;
carry_out : out std_logic
);
end half_adder;

architecture arc_HA of half_adder is
begin
sum_out <= input1 xor input2;
carry_out <= input1 and input2;
end arc_HA;
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Full adder using Half adder code :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity full_adder is
port (
input1 : in std_logic;
input2 : in std_logic;
   carry_in : in std_logic;
--
sum_out : out std_logic;
carry_out : out std_logic
);
end full_adder;

architecture arc_FA of full_adder is

component half_adder is
port (
input1 : in std_logic;
input2 : in std_logic;
--
sum_out : out std_logic;
carry_out : out std_logic
);

signal cout_sig_1, cout_sig_1, sum_sig : std_logic ;

end component;
begin

U_fa1 : half_adder port map ( input1, carry_in, sum_sig, cout_sig_1);
U_fa2 : half_adder port map ( input2, sum_sig, sum_out, cout_sig_2);
assign carry_out = cout_sig_1 or cout_sig_2 ;
end arc_FA;
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4 bit Full adder using Full adder code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fA_4bit is
port (
input1 : in std_logic_vector(3 downto 0);
input2 : in std_logic_vector(3 downto 0);
   carry_in : in std_logic;
--
sum_out : out std_logic_vector(3 downto 0);
carry_out : out std_logic
);
end fA_4bit;

architecture arc_4bit_FA of fA_4bit is

component full_adder is
port (
input1 : in std_logic;
input2 : in std_logic;
   carry_in : in std_logic;
--
sum_out : out std_logic;
carry_out : out std_logic
);
end component;

signal sum_out : std_logic_vector( 2 downto 0 ) ;
signal cout_sig : std_logic_vector ( 1 downto 0 );

end component;
begin
  
  
U_fa1 : full_adder port map ( input1(0), input2(0), '0', sum_out(0), cout_sig(0) );
U_fa2 : full_adder port map ( input1(1), input2(1), cout_sig(0), sum_out(1), cout_sig(1) );
U_fa3 : full_adder port map ( input1(2), input2(2), cout_sig(1), sum_out(2), cout_sig(2) );
U_fa4 : full_adder port map ( input1(3), input2(3), cout_sig(2), sum_out(3), carry_out );

end arc_4bit_FA;
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16bit Full adder using 4 bit full adder code :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fa_16bit is
port (
input1 : in std_logic_vector(15 downto 0);
input2 : in std_logic_vector(15 downto 0);
   carry_in : in std_logic;
--
sum_out : out std_logic_vector(15 downto 0);
carry_out : out std_logic
);
end fa_16bit;

architecture arc_16bit_FA of fa_16bit is

component fA_4bit is
port (
input1 : in std_logic_vector(3 downto 0);
input2 : in std_logic_vector(3 downto 0);
   carry_in : in std_logic;
--
sum_out : out std_logic_vector(3 downto 0);
carry_out : out std_logic
);
end component;

signal sum_out : std_logic_vector( 2 downto 0 ) ;
signal cout_sig : std_logic_vector ( 1 downto 0 );

end component;
begin
  
  
U_16fa1 : fA_4bit port map ( input1(3 downto 0), input2(3 downto 0), '0', sum_out(3 downto 0), cout_sig(0) );
U_16fa2 : fA_4bit port map ( input1(7 downto 4), input2(7 downto 4), cout_sig(0), sum_out(7 downto 4), cout_sig(1) );
U_16fa3 : fA_4bit port map ( input1(11 downto 8), input2(11 downto 8), cout_sig(1), sum_out(11 downto 8), cout_sig(2) );
U_16fa4 : fA_4bit port map ( input1(15 downto 12), input2(15 downto 12), cout_sig(2), sum_out(15 downto 12), carry_out );

end arc_16bit_FA;
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Test bench code for 16 bit adder :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_bench is
end test_bench;

architecture behave of test_bench is

signal tb_in1, tb_in2, tb_sum_out : std_logic_vector(15 downto 0);
signal tb_carry_in, tb_carry_out : std_logic ;
  
component fa_16bit is
port (
input1 : in std_logic_vector(15 downto 0);
input2 : in std_logic_vector(15 downto 0);
   carry_in : in std_logic;
--
sum_out : out std_logic_vector(15 downto 0);
carry_out : out std_logic
);
end component;
begin

UU : fa_16bit port map ( tb_in1, tb_in2, tb_carry_in, tb_sum_out, tb_carry_out );

process is
begin
tb_in1 <= "0000";
tb_in2 <= "0000";
   tb_carry_in <= '0';
wait for 10 ns;
tb_in1 <= "0010";
tb_in2 <= "1111";
   tb_carry_in <= '0';
wait for 10 ns;
tb_in1 <= "0010";
tb_in2 <= "1101";
   tb_carry_in <= '0';
wait for 10 ns;
tb_in1 <= "0001";
tb_in2 <= "1111";
   tb_carry_in <= '0';
wait for 10 ns;
end process;
end behave;

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