Question

A pulse-generating circuit generates eight repetitive pulses as shown in the figure. Implement the pulse-generating circuit using the counter circuits listed and a minimum of gate logic. Use J-K flip-flops for the counters that trigger on the falling edge of a clock that has a frequency eight times the frequency of one of the pulses. The pulses must be free of glitches; explain any restrictions on the propagation delays of gates and flip-flops so that the pulses will be glitch free (a) Ring counter (A ring counter is a shift register with end-to-end feedback.) (b) Johnson counter C) Binary counter To TI T2 T: T4 T5 T6

Answer 1

ND espellkve Pule I m plemont Note lst shef haru ogge mod

age No (2 * faling edge toeggoud Req Counter) (8ff) --> 010 5

clock 6 ck

Jhonson Counte 2 k G k G Clk ータ Benay Counter 위. Pio