Question

2. For the following digital design, (15%) Construct a state table, including output z Minty ritea Booleanexpress ons needed first. (10%) Complete the timing diagram for z. Assume flip-flop output is 0 initially. a. b. MUX 4i Clock Clock

Answer 1

Here let's start with initial condition that is q=0. Flip flop is negative edge triggered, so output will change when clock pulse will change from 1 to 0. And here Z=q(t).

Clock pulse 1: a=0 ,b=0 so D=Z=q(t), and q=0 initially, so now D=0, so now q(t)=0=Z.

Clock pulse 2: a=1, b=1 so D=a=1, now q(t)=0(because D was 0 in last pulse so when pulse changes output also changes and according to D flip flop output will be same as previous D value(bit).)

Clock pulse 3: a=1, b=1 so D=a=1, now q(t)=1.

Clock pulse 4:a=1, b=0 so D=Z=q(t)=1, because now q(t)=1(because D was 1 in last pulse) .

Clock pulse 5:a=0, b=0 so D=Z=q(t)=1,reason:now q(t)=1(because D was 1 in previous pulse).

Clock pulse 6:a=1, b=1 so D=a=1, now q(t)=1.

Now let's make state table and timing diagram:

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