Given four-input Boolean functions,
F1 (A,B,C,D) = Σm(4, 5, 10, 11, 12)
F2 (A,B,C,D) = Σm(0, 1, 3, 4, 8, 11)
F3 (A,B,C,D) = Σm(0, 4, 10, 12, 14)
(a) Realize F1, F2 and F3 using a ROM.
(b) Realize F1, F2 and F3 using a PLA of minimum size. Show the PLA table and location of switches.
Given four-input Boolean functions, F1 (A,B,C,D) = Σm(4, 5, 10, 11, 12)
Procedure Given the following switching functions with four inputs, a, b, c, and d and three outputs, F2, F1, Fo, F2 (a, b,c,d) = Em (3,4,6,9, 11) F (a, b, c, d) =m (2, 4, 8, 10, 11, 12) Fo (a, b, c, d) =ăm (4, 6, 9, 14, 15) 1. Design the switching functions using 8:1 MUXs. 2. Design the switching using 4:16 Decoder and minimal logic gates. 3. Design the switching functions using a ROM. 4. Design a...
Exercise 2: Show a design for the following Boolean functions using the simple 4-input, 4 output PAL shown below. Observe that the simple PAL has active high outputs- that is, the outputs of the OR gates are not inverted. (Hint: Try to simplify the functions) F1(A, B, C, D) m (6,7,9,11,12,13) F2(A, B, C, D)-m(0,2,3,4,5,10,11,13,15) F3(A, B, C, D)-m(2,3,6,7,10,11,14,15) A B C D FI F2 F3 F4 March 6, 2019
Computer architecture Having the next Boolean functions: F1(x,y,z)-П (1, 3, 5) . F2(x,y,z)-Σ (0, 2, 4, 5) . 1. Make one logic gate design circuit, using AND, OR and NOT logic gates (20 points). 2. Design two 4-to-1 selectors, one for each Boolean function (20 points) 3. Design one 3-to-8 decoder to solve both Boolean functions (20 points) 4. Design a 8x2 ROM to solve both Boolean functions (20 points) 5. Design a 3x5x2 PLA to solve both Boolean functions...
Problem 1 Write the output functions of the PLA circuit given at the left. a. F1 b. F2 c. F3 Problem 1 Write the output functions of the PLA circuit given at the left. a. F1 b. F2 c. F3
(a) Implement the following Boolean functions using decoders. i) F1 = x'y z' + x Z ii) F2 = x y' z' + x' y (b) Implement the following Boolean function using multiplexers. i) F1 (a, b, c, d) = Σ(1, 3, 4, 11, 12, 13, 14, 15) ii) F2 (a, b, c, d)= Σ(1, 2, 5, 7, 8, 10, 11, 13, 15)
(10 Points) Realize F, and F, using a PLA. Fi(a,b,c,d) = m(1,2,4,5,6, 8, 10, 12, 14) F2(a, b, c, d) = m(2, 4, 6, 8, 10, 11, 12, 14, 15)
The functions are: f1(a,b,c,d) = ∑m(0,1,3,6,9,11) , f2(a,b,c,d) = Πm(2,3,4,5,7,10,11,12,13,14,15) and f3(a,b,c,d) = ab’c’ + a’b’c +b’cd Complete the following problems for functions f1, f2, and f3 1. Implement the 3 functions on one(1) 4x16 decoder
1. (15 pts) Simplify the following Boolean functions using K-maps: a. F(x,y,z) = (1,4,5,6,7) b. F(x, y, z) = (xy + xyz + xyz c. F(A,B,C,D) = 20,2,4,5,6,7,8,10,13,15) d. F(A,B,C,D) = A'B'C'D' + AB'C + B'CD' + ABCD' + BC'D e. F(A,B,C,D,E) = (0,1,4,5,16,17,21,25,29) 2. (12 pts) Consider the combinational logic circuit below and answer the following: a. Derive the Boolean expressions for Fi and F2 as functions of A, B, C, and D. b. List the complete truth table...
Question #7 12 points Implement the following functions using: X(A,B,C,D) = X (3,7,11,14,15) Y(A, B,C,D) = {(3,4,5,7,11,15) Z(A, B, C,D) = {(1,5, 14, 15) a) a single 16 x 3 ROM (use dot notation to indicate the ROM contents) b) a 4 x 4 x 3 PLA (use dot notation)
[10] A combinational circuit is specified by the following three Boolean function: F1(A,B,C) = {(2,4,7) F2(A, B, C) = 2(0,3) F3(A,B,C) = {(0,2,3,4,7) Implement the circuit with a decoder constructed with NAND gates and NAND or NOR gates connected to the decoder outputs. Use block diagram for the decoder. Minimize the number of inputs in the external gates.