6(10%) (Pipelining) Suppose you have a system where every problem must pass through 4 pipeline stages with delays of 30...
6(10%) (Pipelining) Suppose you have a system where every problem must pass through 4 pipeline stages with delays of 30ns, 60ns, 15ns, 20ns. Each stage cannot be replicated, but can be pipelined. (a) What is the minimum number of stages, from beginning to end,in a pipeline that has no load imbalance? (b) What is the clock cycle time for this case, assuming clock to q delay, setup time and hold time is 2ns for registers?
6(10%) (Pipelining) Suppose you have a system where every problem must pass through 4 pipeline stages with delays of 30ns, 60ns, 15ns, 20ns. Each stage cannot be replicated, but can be pipelined. (a) What is the minimum number of stages, from beginning to end,in a pipeline that has no load imbalance? (b) What is the clock cycle time for this case, assuming clock to q delay, setup time and hold time is 2ns for registers?