A Y = A ® B 1 1 1 0 0 1 1 1 Apply the idea of the truth table above and design a 3-bit comparator using XOR or XNOR gat...
A Y = A ® B 0 1 1 1 0 1 1 1 Apply the idea of the truth table above and design a 3-bit comparator using XOR or XNOR gates of your choice. The design should be able to determine the equality between two 3-bit words. An LED should be turned ON only when every bit in "Word A" matches every corresponding bit in "Word B".Otherwise, the LED has to be OFF Hint for I/O port Definitions: MSB...
A Y = A+ B 1 1 1 1 1 1 Apply the idea of the truth table above and design a 3-bit comparator using XOR or XNOR gates of your choice. The design should be able to determine the equality between two 3-bit words. An LED should be turned ON only when every bit in "Word A" matches every corresponding bit in "Word B". Otherwise, the LED has to be OFF Hint for I/O port Definitions: Port Name MSB...
A Y = A ® B 1 1 1 1 1 Apply the idea of the truth table above and design a 3-bit comparator using XOR or XNOR gates of your choice. The design should be able to determine the equality between two 3-bit words. An LED should be turned ON only when every bit in "Word A" matches every corresponding bit in "Word B". Otherwise, the LED has to be OFF Hint for I/O port Definitions: Port Name Direction...
9) (2 points) You are given two, 3-bit, two's complement integers A[2:0, B(2 : 0). You are asked to design a two's complement (signed) comparator circuit that produces f = 1 when A > B; otherwise f = 0. Design the above circuit (block diagram) assuming that you are given: i) pre-designed 3-bit unsigned comparators (f = A > B), ii) MUXes, and iii) any AND/OR/XOR/NOT Boolean logic gates.
Some questions may require well bulum 1. HDL stands for? a. Hardware Design Language b. Hardware Development Language c. Hardware Description language d. Hot Dry Land 2. What is the basic building unit of a VHDL design? a. Blocks b. Cubes c . Dices d. Bricks 3. What reserved word do all VHDL entities end with? a. entity b. use c. port d. end d. IEEE 4. Which block describes a design's interface? a. entity b. architecture c. library 5....
please answer question 4 (all parts of question4 please) will rate! 3. (30 pts) Design a 2-bit Gray code generator that ropetitively delivers the sequence 00301911-10-00when the input signal UP- 1,or in reverse order 009 10기け01 →00→ when UP-0. Your design should include an asynchronous low. active reset operation: the FSM goes to 00 state when a reset signal is applied In addition to the state output z[1). 2[0]. there is a carry/borrow output bit e which is I when...
6. Design a 2-bit binary counter that counts, 0, 1, 2, 3, 0,. Use the 74LS374 IC, which has eight D flip-flops on it. They are positive-edge triggered, but it will not matter at all here You may draw a state diagram and then fill in the table Present State Q(t) Next State (D(t) - Q(t+1)) Q1(t) Qo(t) 7. Design a BCD binary counter that counts from 0 to 9 then back to 0 and repeat, displaying the count on...
all please Design a 3-bit counter that has only one input, w. It counts down 7, 6,5,... 0, 7,.. whenever w-0, and counts up 0,1,2...7,0... when w 1 The output z-1, when the state of the counter is a prime number. Otherwise, z-0 1. List Inputs, Outputs and the count sequence. (5pts) 2. Draw the finite State machine for the counter. (10pts) 3. Draw the state transition table <extra columns for the flip flops values> (20pts) armed resource/content/1/case%20study.template.docx 4. Design...
1. (15 pts) Simplify the following Boolean functions using K-maps: a. F(x,y,z) = (1,4,5,6,7) b. F(x, y, z) = (xy + xyz + xyz c. F(A,B,C,D) = 20,2,4,5,6,7,8,10,13,15) d. F(A,B,C,D) = A'B'C'D' + AB'C + B'CD' + ABCD' + BC'D e. F(A,B,C,D,E) = (0,1,4,5,16,17,21,25,29) 2. (12 pts) Consider the combinational logic circuit below and answer the following: a. Derive the Boolean expressions for Fi and F2 as functions of A, B, C, and D. b. List the complete truth table...
3) (30 points) Given three 8-bit unsigned inputs A, B, C, design a circuit that outputs 1 if the smallest absolute distance between any pair of values is less than 15 or greater than 50. Note: your circuit must work for any 8-bit unsigned numbers given in A, B, C. 18 18 18 - Assume that you have the following Datapath components available (unsigned only) - decoders, encoders, muxes, parallel load registers, adders, A B C subtractors, magnitude comparators, array...