Question

Explain the roles of the resistors in the gates of the Experiments 5.3 to 5.8.Especially discuss what happen if each of them is too large or too small

RC RA Output Y Input A RB Figure 3. (5.3)Logic inverter circuit (NOT gate) +5 V Input A D1 R Input B D2 Output Y Figure 4. (5.4) AND gate circuit Input A D1 Output Y Input B D2 Figure 5. (5.5) OR gate circuit +5 V RC Output Y Input A D1 w A Input B D2 RB Figure 6. (5.6) NOR gate circuit 24 +5 V RA RC Output Y Input A D1 RB Input B D2 Figure 7. NAND gate circuit Vcc (+5 V) RC Input A o- Output Y Input B Input C o- RB Figure 8. TTL gate circuit RA

Answer 1

Figure 5.3) NOT gate:

The basic operation of a NOT gate is to invert the input signal and that is why it is called an inverter. If the input is active low or 0, the output will be active high or 1 and vice versa. In the circuit of figure 5.3 let us Vcc=+5V. Let us apply a high input voltage at A high enough(more than its base potential) to make the transistor ON. As soon as the transistor becomes ON, the supply voltage Vcc(+5V) will get a path to the earth through the resistor RC. At ON condition the transistor will behave short-circuited ideally, hence entire supply voltage will drop across resistor RC and no voltage will appear at Y and hence the output of the inverter or NOT gate will be zero. In the actual case, there will be some voltage drop across collector and emitter even at ON condition of the transistor.

Now, applying an active low or 0 at the input A, at that condition, as the base of the transistor is at 0 potential, the transistor will be in OFF condition and hence the supply voltage will not get any path to the earth and entire supply voltage will appear at output terminal of the NOT gate, high or logical 1 when input terminal A is low or logical zero.

Figure 5.4) AND gate:

We know the working of a basic AND gate that its output will be high or logic 1 only in the case if both the inputs are high and will be low or logic 0 in when any inputs are 0. In the circuit shown in the figure if either input A or B is at ground potential (logic 0), then due to the higher potential on the anode side due to the positive voltage (+5 volts) from resistor R which is more than the knee voltage for a diode, current will flow through the diodes and the voltage on the output will be equal to the forward voltage of diode.

If both inputs to the AND gate are high (logic 1), then no current will pass through either diode, and the positive voltage through R will appear on the output Y.

Figure 5.5) OR gate:

   We know the working of a basic OR gate that its output will be low only in case if both inputs are active low or logic 0 and output will be high if any inputs are 1. In the case of the OR gate, if there is no potential (i.e. logic 0, or ground) on both inputs, no current will pass through either diode, and the resistor R will keep the output at the ground (active low or logic 0).

If either of the inputs has a positive (logic 1 or high state) voltage on its inputs, then current will pass through the diodes and appear on the output Y, less the forward voltage of the diode.

Figure 5.6) NOR gate:

The basic operation of a NOR gate is opposite of OR gate i.e. when both the inputs are active low or 0 then the output will be 1 and will be 0 in any other case. As can be seen in the circuit of NOR gate and NOT gate they are almost identical except that in the case of NOR gate the input is a combination of both inputs, so the working of this gate is similar to NOT gate. When both the inputs are low, the input to the transistor is less than its base potential and the transistor becomes OFF and all the voltage appears at Y and output will be 1 or active high. And it will be low in any other case.

Figure 5.7) NAND gate:

The operation of the NAND gate is exactly opposite to that of AND gate. The output of the NAND gate will be low only if both the inputs are active high or 1 and will be zero in any other case. Let us assume that both inputs A and B in the circuit of figure 7 are high, then both the diodes will be reversed biased due to the positive voltage at their anode by resistor RA. Due to this reverse bias, the voltage at the base of the transistor will be approx +5 volt caused by RA which will put the transistor in ON condition and in this condition whole supply voltage will appear at the terminals of resistor RC and the output at Y will be low.

In any other case, at least one diode will be forward biased so the input to the transistor will be less than its base potential and therefore it will be in OFF condition so the supply voltage will occur at the output terminal Y.

Figure 5.8) TTL gate:

TTL stands for Transistor-Transistor Logic. In figure 8, the circuit given is TTL NOR gate. Its basic operation is similar to a NOR gate i.e. if any of the inputs are high the output will be low otherwise the output will be high.

When one of the inputs is low, the easiest path to ground through the corresponding RA resistor is through the base of the transistor below it and to the input. This brings the transistor's collector voltage low enough so that very little current can flow through the base of the transistor on the right. This keeps that transistor off. If both inputs are low, both transistors connected to the output are off, and the output stays at 5 V.

When one of the inputs is high, the transistor to the right of it is in the reverse-active state. A current flows through the RA resistor through the base and collector of these transistors, and then through the base of the transistor on the right, saturating it and bringing the output down near the ground.