Question

Q1,Q2 and Q3

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Question Consider the following inverter design problem: Given VpD 5V, k' 30uA/V , and Vo 1V, design a resistive-load inverter circuit with VoL 0.2V . Specifically, determine the (W/L) ratio of the driver transistor and the value of the load resistor RL that achieve the required VoL- (10 marks) Question 2 Consider a pseudo-nMOS NOR2 gate, with the following parameters: 1V., Vro,load -31V, y = 0.4V1/2, andl F|= 0.6V. The transistor Hn Cox =254A/V2, Vro,driver W W 4, and (Load 1/3. The power supply voltage is VpD dimensions are given as A2, ) - 5V.Calculate the output voltage levels for all four valid input voltage combinations. (10 marks) 0 3:-Comprehends the architecful 1 miorocontroler (PLO1) Cenrs /15 4:-Examine the assembiy ianguages rams for 8051 microcontroler and as 37 odules (PL02) Cace / 52 Question 3 Consider the soft-node structure shown in Figure Q3, which consists of the drain (or source, depending on current direction) terminal of the pass transistor, connected to the polysilicon gate of an nMOS driver transistor via a metal interconnect. Determine the worst case (minimum) hold time for the soft node with the following parameters: VTo 0.8 V y=0.4 V2 20F1=0.6 V Ce 0.065 F/um2 Cmaal 0.036 fF/um2 Cpady 0.055 fF/um2 Cjo 0.095 1F/um2 Cjo=0.2 fF/um soft node Mpass M1 V. скг C Figure Q3 (10

Answer 1

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