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7U. Write Verilog code that implements the 3-way T-intersection with each side having red, yellow and green lights. Assume th
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// Problem 1S. f(A,B,C) = A’.B.C + A.B.C.

//-------------------------------------------------------------------------------------------------

`timescale 1 ns / 1 ps

module prob6s (A, B, C, f);

input A, B, C;

wire A, B, C;

output f;

reg f;

always @ (A, B, C) begin

f = (~A)&B&C | A&B&C; //Use logical or “|”, and “&”, not “~”

end

endmodule

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