Question

4.27 Suppose the following command sequence is run on a five-step pipeline data pass.

ADD X5, X2, X1

LDUR X3, [X5, #4]

LDUR X2, [X2, #0]

ORR X3, X5, X3

STUR X3, [X2, #0]

1.Change or reorder the code to minimize NOP operations. Assume that register X7 can be used to store temporary values in the modified code.

2. What would happen if this code were executed in a process with forward transmission but without a sub-sea detection unit?

Answer 1

Answer :1:

Pipeline Stages

• Stage 1 (Instruction Fetch)
  In this stage the CPU reads instructions from the address in the memory whose value is present in the program counter.
• Stage 2 (Instruction Decode)
  In this stage, instruction is decoded and the register file is accessed to get the values from the registers used in the instruction.
• Stage 3 (Instruction Execute)
  In this stage, ALU operations are performed.
• Stage 4 (Memory Access)
  In this stage, memory operands are read and written from/to the memory that is present in the instruction.
• Stage 5 (Write Back)
  In this stage, computed/fetched value is written back to the register present in the instructions.

2 Answer : To improve the performance of a CPU we have two options:
1) Improve the hardware by introducing faster circuits.
2) Arrange the hardware such that more than one operation can be performed at the same time.

Since, there is a limit on the speed of hardware and the cost of faster circuits is quite high, we have to adopt the 2^nd option.

Code Development Flow to Increase Performance

If this code were executed in a process with forward transmission but without a sub-sea detection unit due to use following :
The recommended code development flow involves utilizing the ’C6000 code generation tools to aid in your optimization rather than forcing you to code by hand in assembly Let the compiler do all the laborious work of instruction selection, parallelizing, pipelining, and register allocation, and you focus on getting the product to market quickly. Because of these features, maintaining the code becomes easy, as everything resides in a C framework that is simple to maintain, support and upgrade.We  can achieve the best performance from your ’C6000 code if you follow this code development flow when you are writing and debugging your code:

Code Development Steps

Compile and profile native C/C++ code

1 Validates original C/C++ cod

2 .Determines which loops are most important in terms of MIPS requiremen

Add const declarations, loop, memory bank, and data alignment information

Reduces potential pointer aliasing problems

Allows loops with indeterminate iteration counts to execute epi

Uses pragmas to pass count information to the compiler

Uses memory bank pragmas and _nassert intrinsic to pass memory bank and alignment information to the compiler.

Optimize C code using other ’C6000 intrinsics and other methods

Facilitates use of certain ’C6000 instructions not easily represented in c code

Write linear assembly

Allows control in determining exact ’C6000 instructions to be used

Provides flexibility of hand-coded assembly without worry of pipelining, parallelism, or register allocation

Can pass memory bank information to the tools

Uses .trip directive to convey loop count

Add partitioning information to the linear Assembly

Can improve partitioning of loops necessary

Can avoid bottlenecks of certain hard

Memory alias disambiguation

Memory alias disambiguation analyzes whether a dependence, through a memory location, exists between a given pair of instructions. Dependences between instructions are then used to determine the fastest legal schedule of those instructions

Data Dependence Between Instructions

One dictionary definition of dependence is “the state of being determined, influenced, or controlled by something else”. In the world of software, the objects being influenced can be modules of code, specific functions, blocks within functions, individual statements, data structures, variables, etc. Further, the relationship can be interdependent, for example, two objects can depend on each other. This appendix refers to only one kind of dependence relationship: the data dependence between individual assembly language instructions. At this level, dependence is evaluated between pairs of instructions. Two instructions have a dependence when they reference (read or write) the same machine resource, for example, register, memory location, status bit, and so forth. So, a dependence is characterized by the following pieces of information

The first instruction

The second instruction

The resource both instructions reference

The first instruction reference - read or write?

The second instruction reference - read or w

For example: I1: ADDK 10,A2 ;

I2: STW A2,*

Dependence Graphs

Dependence graphs are used to represent the dependences between a set of instructions.

From the C fragment: a = b + c;

d = e + f;

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