Solutions For Digital Design Chapter 5 Problem 26P

The JK flip-flop has two inputs J and K and the output is termed as Q. The complement of output Q is called as Q’. A clock input C is given to the flip-flop.

The characteristic equation for the JK flip-flop is given by:

Where, is the next output state of the JK flip-flop.

(a) When Q = 0 the characteristic equation becomes,

When Q = 1, the characteristic equation becomes,

The HDL description of the JK flip-flop on considering the characteristic equation when Q = 0 or Q = 1 is shown below:

module JK_FF_a (output reg Q, Q_next, input J, K, CLK, reset_b);

always @ (posedge CLK, negedge reset_b)

if (reset_b == 0) Q <= 0; else

if (Q == 0) Q <= J;

else Q <= ~K;

endmodule

The simulation output waveform of the above HDL description is shown below:

(b) We can analyse the effect of JK inputs on the output of the flip-flop at each clock trick by the following HDL description:

module JK_FF_b (output reg Q, input J, K, CLK, reset_b);

always @ (posedge CLK, negedge reset_b)

if (reset_b == 0) Q <= 0;

else

case ({J, K})

2'b00: Q <= Q;

2'b01: Q <= 0;

2'b10: Q <= 1;

2'b11: Q <= ~Q;

endcase

endmodule

module t_JK_FF_b ();

wire Q_a, Q_b;

reg J, K, clk, reset_b;

JK_FF_a M0 (Q_a, J, K, clk, reset_b);

JK_FF_b M1 (Q_b, J, K, clk, reset_b);

initial #100 $finish;

initial begin clk = 0; forever #5 clk = ~clk; end

initial fork

#2 reset_b = 1;

#3 reset_b = 0;

#4 reset_b = 1;

J =0; K = 0;

#20 begin J= 1; K = 0; end

#30 begin J = 1; K = 1; end

#50 begin J = 1; K = 1; end

join

endmodule

The simulation output waveform is shown below: