There are two kinds of procedural assignments in a Verilog.
• Blocking statements ( = )
• Non-blocking statements ( <= )
Blocking statements are executed sequentially in the order that they are listed. They have an immediate effect on the contents of memory before the next statement execution.
Non-blocking statements are executed concurrently without regard to order that they are listed.
Refer to the Verilog & VHDL code using blocking statements.
From the first statement, Reg A contains the value of 125.
From the second statement, Reg B contains the value of 125.
Therefore, the value of Reg A and Reg B are respectively.
Refer to the Verilog & VHDL code using Non-blocking statements.
All the statements considered RegA = 50 initially.
From the first statement, Reg A replaces the value 50 with the new value 125. So, Reg A contains the value of 125.
From the second statement, Reg B contains the value of 50 since all the statements executes concurrently with register initial value RegA = 50.
Therefore, the value of Reg A and Reg B are respectively.