Include a synchronous clear input to the register of Fig. 6.2 . The modified register wi...

Include a synchronous clear input to the register of Fig. 6.2 . The modified register will have a parallel load capability and a synchronous clear capability. The register is cleared synchronously when the clock goes through a positive transition and the clear input is equal to 1. (HDL—see Problem 6.35(a), (b).)