(Flip-Flops) Given the input and clock transitions in Figure 1, indicate the output of a D...

(Flip-Flops) Given the input and clock transitions in Figure 1, indicate the output of a D device assuming:

(a) It is a negative edge-triggered flip-flop.

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(b) It is a master–slave flip-flop.

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(c) It is a positive edge-triggered flip-flop.

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(d) It is a clocked latch. You may assume 0 setup, hold, and propagation times.

Figure 1

Timing diagram.