(Clocking Issues) Given the sequential-logic circuit of Figure 1, where the flip-flops hav...

(Clocking Issues) Given the sequential-logic circuit of Figure 1, where the flip-flops have worst-case setup times of 20 ns, propagation delays of 13 ns, and hold times of 5 ns, answer the following questions:

(a) Assuming 0 propagation delay through the combinational- logic block, what is the maximum allowable frequency of the clock that controls this subsystem?

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(b) Assuming a typical combinational-logic delay of 75 ns and a worst-case delay of 100 ns, how does your answer to part (a) change?

Figure 1

Sequential circuit.