Compile and simulate the 4-bit adder in Figure. Apply combinations that check out the righ...

Compile and simulate the 4-bit adder in Figure. Apply combinations that check out the rightmost full adder for all eight input combinations; this also serves as a check for the other full adders. Also, apply combinations that check the carry chain connections between all full adders by demonstrating that a 0 and a 1 can be propagated from C0 to C4.

Figure Hierarchical Dataflow/Structural Verilog Description of 4-Bit Adder