The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solut...

The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solution is available on the text website.

+ Using Figure 1 as a guide and a “when-else” on S from Figure 2, write a high-level behavior VHDL description for the adder–subtractor in Figure 3 (see Figure 4 for details). Compile and simulate your description. Assuming a ripple carry implementation, apply combinations that check out one of the full adder–subtractor stages for all 16 possible input combinations. Also, apply combinations to check the carry chain connections in between the full adders by demonstrating that a 0 and a 1 can be propagated from C0 to C4. Check the overflow signals as well.

Figure 1 Behavioral Description of 4-Bit Adder

Figure 2 Conditional Dataflow VHDL Description of 4–to–1-Line Multiplexer Using When-Else

Figure 3 Overflow Detection Logic for Addition and Subtraction

Figure 4 Hierarchical Structural/Dataflow Description of 4-Bit Full Adder