Question

7. (a) If we had a small bank of memory with 64 addressable locations, how many bits would we need for the address? (b) What

0 0
Add a comment Improve this question Transcribed image text
Answer #1

10 4 bitオ For 32 6 bitオ Q 128 3 2 For normal dacimal numbes

Add a comment
Know the answer?
Add Answer to:
7. (a) If we had a small bank of memory with 64 addressable locations, how many...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions
  • Memory organization a) Suppose that a 32MB system memory is built from 32 1MB RAM chips. How many...

    Memory organization a) Suppose that a 32MB system memory is built from 32 1MB RAM chips. How many address lines are needed to select one of the memory chips? Suppose a system has a byte-addressable memory size of 4GB. How many bits are required for each address? Suppose that a system uses 16-bit memory words and its memory built from 32 1Mx 8 RAM chips. How large, in words, is the memory on this system? Suppose that a system uses...

  • ​Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64 bytes each

    Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64 bytes each, and 4-page frames. Assuming the following page table, answer the questions below: Page #Frame #Valid Bit0111312-03014215-06-07-0a) How many bits are in a virtual address? b) How many bits are in a physical address? c) What physical address corresponds to the following virtual addresses (if the address causes a page fault, simply indicate this is the case)? 1) Ox00 2) 0x44 3) OxC2 4) 0x80

  • Please help me with this computer architecture problem (a) How many byte offset bits are required...

    Please help me with this computer architecture problem (a) How many byte offset bits are required in the address to reference 1024 words of data when the word size is 128 bits? (b) What is the total capacity of memory that is addressable using 48-bit word addresses (assume each data word is 32 bits).

  • Question 2 Suppose you have a byte-addressable virtual address memory with 8 virtual pages of 64...

    Question 2 Suppose you have a byte-addressable virtual address memory with 8 virtual pages of 64 bytes each and 4 page frames. Assuming the following page table, Page = Frame Valid Bit 0 0 1 2 3 4 5 What physical address corresponds to the virtual address 0X44 a. OXC1 b.OXC2 COXC4 d. OXCO OXC3

  • a) Suppose we have a 64 KB, direct-mapped cache with 8-word blocks. Determine how many bits...

    a) Suppose we have a 64 KB, direct-mapped cache with 8-word blocks. Determine how many bits are required for the tag, index, and offset fields for a 32-bit memory address. b) If instead, we use a 64 KB, 4-way set-associative cache with 8-word blocks, how many bits will be required for the tag, index, and offset fields for a 32-bit address? c) What type of cache is shown in problem 2? How many bits are required for this cache’s tag,...

  • 1. For a 512 k × 32 memory system, how many unique address locations are there?...

    1. For a 512 k × 32 memory system, how many unique address locations are there? Give the exact number. 2. For a 512 k × 32 memory system, what is the capacity in bits? 3. For a 512 k × 32 memory system, how wide does the incoming address bus need to be in order to access every unique address location?

  • Assume the following about a computer with a cache: .. The memory is byte addressable. •...

    Assume the following about a computer with a cache: .. The memory is byte addressable. • Memory accesses are to 1-byte words (not to 4-byte words). .. Addresses are 8 bits wide. .. The cache is 2-way associative cache (E=2), with a 2-byte block size (B=2) and 4 sets (5=4). • The cache contents are as shown below (V="Valid"): Set #Way #0 Way #1 V=1;Tag=0x12; Data = v=1;Tag=0x10; Data = Ox39 0x00 0x26 Ox63 V=1;Tag=0x09; Data = v=1;Tag=0x11; Data =...

  • 18. You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associati...

    18. You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame. Given the system state as depicted above, answer the following questions: a) How many bits are in a virtual address...

  • This problem concerns a physical memory cache. Recall that m is the number of physical address...

    This problem concerns a physical memory cache. Recall that m is the number of physical address bits, C is the cache size (number of bytes), B is the block size in bytes, E is the associativity, S is the number of cache sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Suppose we have a cache with the following characteristics m = 32 C...

  • Problem #1 (25 points) Address Space, Memory Consider a hypothetical 18-bit processor called HYP18 with all...

    Problem #1 (25 points) Address Space, Memory Consider a hypothetical 18-bit processor called HYP18 with all registers, including PC and SP, being 18 bits long. The smallest addressable unit in memory is an 8-bit byte. A. (4 points) What is the size of HYP18's address space in bytes and KB? How many address lines does HYP18 require? Address space: Bytes Address space: KB (KiloBytes). Address bus lines: B. (6 points) Assume that first quarter of the address space is dedicated...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT