1. Which metric measures the number of times the CPU can find something in the cache?...
1. Which metric measures the number of times the CPU can find something in the cache?
a) hit rate
b) miss penalty
c) cache size
d) miss rate
e) hit time
Homework Answers
metric measures the number of times the CPU can find something in the cache is hit rate
a) hit rate
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1. Which metric measures the number of times the CPU can find
something in the cache?...
a) Calculate the AMAT for a cache system with one level of cache between the CPU...
a) Calculate the AMAT for a cache system with one level of cache between the CPU and Main Memory. Assume that the cache has a hit time of 1 cycle and a miss rate of 11%. Assume that the main memory requires 300 cycles to access (this is the hit time) and that all instructions and data can be found in the main memory (there are no misses). b) Let us modify the cache system from part (a) and add...
Question 4 (10 pt). One difference between a write-through cache and a write-back cache can be...
Question 4 (10 pt). One difference between a write-through cache and a write-back cache can be in the time it takes to write. During the first cycle, we detect whether a hit will occur, and during the second (assuming a hit) we actually write the data. Let’s assume that 50% of the blocks are dirty for a write-back cache. For this question, assume that the write buffer for the write through will never stall the CPU (no penalty). Assume a...
2. Cache hierarchy You are building a computer system with in-order execution that runs at 1...
2. Cache hierarchy You are building a computer system with in-order execution that runs at 1 GHz and has a CPI of 1, with no memory accesses. The memory system is a split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32 KB each, with a block size of 64 bytes. The memory system is split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32 KB each, with a block...
Base machine has a 2.4GHz clock rate. There is L1 and L2 cache. L1 cache is...
Base machine has a 2.4GHz clock rate. There is L1 and L2 cache. L1 cache is 256K, direct mapped write through. 90% (read) hit rate without penalty, miss penalty is 4 cycles. (cost of reading L2) All writes take 1 cycle. L2 cache is 2MB, 4 way set associative write back. 95% hit rate, 60 cycle miss penalty (cost of reading memory). 30% of all instructions are reads, 10% writes. All instructions take 1 cycle - except reads which take...
4B, 20%) compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI1 Assume main memory access time of 8 cycles Assume 40% instruct...
4B, 20%) compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI1 Assume main memory access time of 8 cycles Assume 40% instructions require memory data access Assume cache access time of I cycle Assume hit rate 0.90 for instructiens, 0.80 for data Assume miss penalty (time to read memory inte cache and from cache to Processor with cache processor) is 10 cycles >Compare execution times of 100-thousand instructions:
4B,...
A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps...
A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps 2. RR: Register read 80 ps 3. ALU: 240 ps 4. MA : memory access: 160 ps (assuming cache) 5. RW : register write : 80 ps There are 5 basic instruction types: 1. LOAD : IFD+RR+ALU+MA+RW 720 ps 2. STORE: IFD+RR+ALU+MA : 640 ps 3. ARITHMETIC: IFD+RR+ALU+RW : 560 4. BRANCH: IFD+RR+ALU : 480 ps 5. MEMOP: IFD+RR+MA+ALU+MA :...
Assume the miss rate of an instruction cache is 3% and the miss rate of the...
Assume the miss rate of an instruction cache is 3% and the miss rate of the data cache is 5%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 120 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 36%. *The size of the tag field-64- (n + m 2). ** The total...
3. 12+2-4 points] We are comparing the two caches in Problem 1 and Problem 2. Suppose both caphes have a hit time of 2 cycles. The cache in Problem 1 has a miss penalty of 15 cycles. The o...
3. 12+2-4 points] We are comparing the two caches in Problem 1 and Problem 2. Suppose both caphes have a hit time of 2 cycles. The cache in Problem 1 has a miss penalty of 15 cycles. The one in Problem 2 has a miss penalty of 25 cycles. Calculate the total time taken (in cycles) for all accesses, for each cache. Which cache is better- the one in Problem 1 or Problem 2? 3. 12+2-4 points] We are comparing...
A computer system has the following memory timing clock cycle (CC) specification: Cache access ti...
A computer system has the following memory timing clock cycle (CC) specification: Cache access time 1 CC, Main memory access time 100 CC, and Virtual memory access time 100,000 CC. Find the ratio of Average Memory Access Times (AMAT) of the following two programs and determine which program executes faster: B5. cache miss rate : 25% Main memory miss rate Program B: Cache miss rate 20% Main memory miss rates 10% 5%
A computer system has the following memory timing...
(a)What is the average memory access time (AMAT) if a cache uses write-back strategy and 20%...
(a)What is the average memory access time (AMAT) if a cache uses write-back strategy and 20% of the data blocks to be swapped out are dirty. Assume that the miss rate is 15%, the hit time of the cache is 1 cycle and the miss penalty is 8 cycles for the data blocks that are not dirty and 20 cycles for those blocks that are dirty. (b) What is the speedup up if we add a “write-buffer” that eliminates 40%...
4B, 20%) compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI1 Assume main memory access time of 8 cycles Assume 40% instructions require memory data access Assume cache access time of I cycle Assume hit rate 0.90 for instructiens, 0.80 for data Assume miss penalty (time to read memory inte cache and from cache to Processor with cache processor) is 10 cycles >Compare execution times of 100-thousand instructions:
4B,...
A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps 2. RR: Register read 80 ps 3. ALU: 240 ps 4. MA : memory access: 160 ps (assuming cache) 5. RW : register write : 80 ps There are 5 basic instruction types: 1. LOAD : IFD+RR+ALU+MA+RW 720 ps 2. STORE: IFD+RR+ALU+MA : 640 ps 3. ARITHMETIC: IFD+RR+ALU+RW : 560 4. BRANCH: IFD+RR+ALU : 480 ps 5. MEMOP: IFD+RR+MA+ALU+MA :...
Assume the miss rate of an instruction cache is 3% and the miss rate of the data cache is 5%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 120 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 36%. *The size of the tag field-64- (n + m 2). ** The total...
3. 12+2-4 points] We are comparing the two caches in Problem 1 and Problem 2. Suppose both caphes have a hit time of 2 cycles. The cache in Problem 1 has a miss penalty of 15 cycles. The one in Problem 2 has a miss penalty of 25 cycles. Calculate the total time taken (in cycles) for all accesses, for each cache. Which cache is better- the one in Problem 1 or Problem 2? 3. 12+2-4 points] We are comparing...
A computer system has the following memory timing clock cycle (CC) specification: Cache access time 1 CC, Main memory access time 100 CC, and Virtual memory access time 100,000 CC. Find the ratio of Average Memory Access Times (AMAT) of the following two programs and determine which program executes faster: B5. cache miss rate : 25% Main memory miss rate Program B: Cache miss rate 20% Main memory miss rates 10% 5%
A computer system has the following memory timing...
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