Question

(b) Complete the timing diagram for the following circuit. Note that the Ck inputs on the two flip-flops are different. ClrN Q. Clock 9í CIEN CLR Ck Q||||Q5 || LDCLR D|| Ck Clock O OOON D2 Clock

Answer 1

→ Flip flops are D-flip flops. for B-flap Hops Qn+1 = D. - from the input is given taken circuit, we can see from Q' [ 0 = Qi] [Da= 0; / Truth table of D-FF CLR DIQQ I Tx I o Cclear). - - 0 I - o D D2 flip flop is flap flop is negative edge trigger positive edge trigger. → [CLR= CION CLR - Clon

Clon clock When ever clon is o then CLR is logic "1" so both flip flop's will be clearto zero (Q, = 0, Q2=0). y And if clon is at logic then CLR is at logic "o". Now flip Hop's starts working At ist and 3rd clock pulses flip flops are clear.

AS & it will flip flop is respond negative edge tagger so at a falling edge of 2nd, 4th and 5th clock pulses, AS Da flip flop is positive edge tragger, it will respond at rising edge of 2nd 4th and 5th clock pulse