Question

(b) Using a timing diagram showing the clk, Q1 and D2 signals, explain the following timing constraints for the circuit shown in Figure 2.1 cqtcd 2 old where tod is the contamination delay of the combinational logic 7 marks reg2 reg1 Combinational D2 logic clk. clk Figure 2.1 (c) In the circuit shown in Figure 2.2, the flip-flops have a clock-to-Q contamination delay of 30 ps and a propagation delay of 80 ps. They have a setup time of 50 ps and a hold time of 60 ps. Each logic gate has a propagation delay of 40 ps and a contamination delay 25 ps. Sketch a timing diagram for the critical path, and calculate the maximum clock frequency. 10 marks] n1 dk Figure 2.2

Answer 1

CLK D2 CLK R2 R1 CLK Q1 D2 ! hold

The register R2 has a hold time constraint. Its input, D2, must not change until some time, T_hold, after the rising edge of
the clock. According to above Figure D2 might change as soon as t_ccq(clock to q contamination delay) + tcd(combinational path contamination delay) after the rising edge of the clock.

Hence we find,

t_ccq + t_cd >= t_hold (proved)

(c)
we know setup time equation

T_clock >= clock propagation delay + combination block delay + setup time

T_clk >= 80 + 3*40 + 50 ps

T_clk min = 250 ps

f_max = 1/T_clk min = 1/250 = 4 GHz (Answer)